MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet - Page 129

• Manufacturer Part Number: MT47H64M8CB-3:B
• Description: IC DDR2 SDRAM 512MBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-3:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
43. The DRAM output timing is aligned to the nominal or average clock. Most output
44. Half-clock output parameters must be derated by the actual
45. MIN(
46.
47.
48. JEDEC specifies using
49. Requires 8
parameters must be derated by the actual jitter error when input clock jitter is
present; this will result in each parameter becoming larger. The following parameters
are required to be derated by subtracting
t
required to be derated by subtracting
(MAX),
ated by subtracting
(MIN). The parameter
t
when input clock jitter is present; this will result in each parameter becoming larger.
The parameter
(MAX) and
subtracting both
HIGH time driven to the device. The clock’s half period must also be of a Gaussian dis-
tribution;
without duty cycle jitter.
falling edges.
t
inputs; thus,
t
(MAX) times
of
window.
43–44). Micron requires less derating by allowing
LZ
RPST (MAX), is derated by subtracting
HP (MIN) is the lesser of
QH =
t
JIT
DQS
t
CL,
DTY
t
HP -
(MIN),
t
LZ
t
will provide a larger
t
CH) refers to the smaller of the actual clock LOW time and the actual clock
DQS
CH
t
t
CK for backwards compatibility.
JIT
t
QHS; the worst case
t
t
HP (MIN) ≥ the lesser of
CK
AVG
t
(MAX),
DTY
LZ
t
AOF (MIN) is required to be derated by subtracting both
ABS
t
ERR
DQ
and
(MAX). The parameter
t
(MIN) -
JIT
(MIN),
5
t
t
t
t
LZ
PER
CL
ERR
PER
RPST (MIN) is derated by subtracting
t
CH
t
DQ
AVG
(MIN) and
CL and
(MAX), while
129
6–10
t
QHS. Minimizing the amount of
t
AVG
(MAX),
AON (MIN); while these following parameters are
must be met with or without clock jitter and with or
t
QH, which in turn will provide a larger valid data out
PER
and
t
t
QH would be the smaller of
when derating clock-related output timing (notes
CH actually applied to the device CK and CK#
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
AON (MAX). The parameter
t
CL
t
JIT
ERR
t
CL
t
t
JIT
AVG
RPRE (MAX), is derated by subtracting
DTY
t
ABS
t
ERR
5PER
AOF (MAX) is required to be derated by
512Mb: x4, x8, x16 DDR2 SDRAM
DTY
are the average of any 200 consecutive CK
(MIN).
(MIN) and
(MIN).
5PER
(MIN):
t
ERR
(MAX):
t
5
AC (MAX),
PER
t
CH
to be used.
t
AC (MIN),
ABS
©2004 Micron Technology, Inc. All rights reserved.
t
t
ERR
t
JIT
t
CH
CL
(MIN).
DTY
AVG
ABS
t
5
t
RPRE (MIN) is der-
DQSCK (MAX),
PER
(MAX), while
(MAX) or
offset and value
and
t
DQSCK (MIN),
t
ERR
t
JIT
DTY
5
t
Notes
CH
PER
t
JIT
t
ABS
HZ
PER