MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet - Page 11

• Manufacturer Part Number: MT47H64M8CB-3:B
• Description: IC DDR2 SDRAM 512MBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-3:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3:
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
M8, M3, M7, N2,
x16 FBGA Ball
N8, N3, N7, P2,
P8, P3, M2, P7,
Number
K7, L7,
F3, B3
J8, K8
L2, L3
K9
K2
K3
R2
L8
FBGA 84-/60-Ball Descriptions – 128 Meg x 4, 64 Meg x 8, 32 Meg x 16
Ball Number
x4, x8 FBGA
F7, G7,
E8, F8
G2, G3
G8
B3
F9
F2
F3
–
RAS#, CAS#,
LDM, UDM
BA0–BA1
Symbol
CK, CK#
A8–A11
A0–A3
A4–A7
(DM)
ODT
WE#
CKE
A12
CS#
Input On-die termination: ODT (registered HIGH) enables termination
Input Clock: CK and CK# are differential clock inputs. All address and
Input Clock enable: CKE (registered HIGH) activates and CKE (registered
Input Chip select: CS# enables (registered LOW) and disables (registered
Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
Input Input data mask: DM is an input mask signal for write data. Input
Input Bank address inputs: BA0–BA1 define to which bank an ACTIVE,
Input Address inputs: Provide the row address for ACTIVE commands, and
Type Description
resistance internal to the DDR2 SDRAM. When enabled, ODT is only
applied to each of the following balls: DQ0–DQ15, LDM, UDM,
LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ0–DQ7, DQS,
DQS#, RDQS, RDQS#, and DM for the x8; DQ0–DQ3, DQS, DQS#,
and DM for the x4. The ODT input will be ignored if disabled via
the LOAD MODE command.
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and DQS/
DQS#) is referenced to the crossings of CK and CK#.
LOW) deactivates clocking circuitry on the DDR2 SDRAM. The
specific circuitry that is enabled/disabled is dependent on the DDR2
SDRAM configuration and operating mode. CKE LOW provides
precharge power-down mode and SELF REFRESH operation (all
banks idle), or active power-down (row active in any bank). CKE is
synchronous for power-down entry, power-down exit, output
disable, and for self refresh entry. CKE is asynchronous for SELF
REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are
disabled during power-down. Input buffers (excluding CKE) are
disabled during self refresh. CKE is an SSTL_18 input but will detect
a LVCMOS LOW level once V
After V
initialization sequence, it must be maintained for proper operation
of the CKE receiver. For proper SELF REFRESH operation, V
be maintained.
HIGH) the command decoder. All commands are masked when CS#
is registered HIGH. CS# provides for external bank selection on
systems with multiple ranks. CS# is considered part of the command
code.
command being entered.
data is masked when DM is concurrently sampled HIGH during a
WRITE access. DM is sampled on both edges of DQS. Although DM
balls are input-only, the DM loading is designed to match that of
DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is
DM for upper byte DQ8–DQ15.
READ, WRITE, or PRECHARGE command is being applied. BA0–
BA1define which mode register including MR, EMR, EMR(2), and
EMR(3) is loaded during the LOAD MODE command.
the column address and auto precharge bit (A10) for READ/WRITE
commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10
LOW, bank selected by BA1–BA0) or all banks (A10 HIGH). The
address inputs also provide the op-code during a LOAD MODE
command.
11
REF
has become stable during the power on and
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignment and Description
DD
is applied during first power-up.
©2004 Micron Technology, Inc. All rights reserved.
REF
must