MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet - Page 23

IC DDR2 SDRAM 512MBIT 3NS 60FBGA

MT47H64M8CB-3:B

Manufacturer Part Number
MT47H64M8CB-3:B
Description
IC DDR2 SDRAM 512MBIT 3NS 60FBGA
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT47H64M8CB-3:B

Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
512M (64M x 8)
Speed
3ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
60-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Figure 9:
Extended Mode Register (EMR)
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
COMMAND
COMMAND
DQS, DQS#
DQS, DQS#
CK#
CK#
DQ
DQ
CK
CK
READ
READ
CAS Latency (CL)
T0
T0
Notes:
1. BL = 4.
2. Posted CAS# additive latency (AL) = 0.
3. Shown with nominal
The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable, output drive strength, on-
die termination (ODT) (R
DQS# enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These
functions are controlled via the bits shown in Figure 10 on page 24. The EMR is
programmed via the LM command and will retain the stored information until it is
programmed again or the device loses power. Reprogramming the EMR will not alter the
contents of the memory array, provided it is performed correctly.
The EMR must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time
tion. Violating either of these requirements could result in unspecified operation.
NOP
NOP
T1
T1
CL = 3 (AL = 0)
CL = 4 (AL = 0)
NOP
NOP
T2
T2
t
AC,
TT
t
), posted AL, off-chip driver impedance calibration (OCD),
DQSCK, and
23
NOP
NOP
T3
T3
D
OUT
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
MRD before initiating any subsequent opera-
DQSQ.
D
n + 1
TRANSITIONING DATA
OUT
512Mb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register (EMR)
NOP
NOP
T4
T4
D
D
n + 2
OUT
OUT
n
D
D
n + 1
n + 3
OUT
OUT
©2004 Micron Technology, Inc. All rights reserved.
NOP
NOP
T5
T5
D
n + 2
OUT
DON’T CARE
D
n + 3
OUT
NOP
NOP
T6
T6

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