MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet - Page 34

• Manufacturer Part Number: MT47H64M8CB-3:B
• Description: IC DDR2 SDRAM 512MBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-3:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DESELECT, NOP, and LM Commands
DESELECT
NO OPERATION (NOP)
LOAD MODE (LM)
Bank/Row Activation
ACTIVE Command
ACTIVE Operation
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in
progress are not affected. DESELECT is also referred to as COMMAND INHIBIT.
The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to
perform a NOP (CS# is LOW; RAS#, CAS#, and WE are HIGH). This prevents unwanted
commands from being registered during idle or wait states. Operations already in
progress are not affected.
The mode registers are loaded via inputs BA1–BA0 and A13–A0 for x4 and x8, and A12–A0
for x16 configurations. BA1–BA0 determine which mode register will be programmed.
See “Mode Register (MR)” on page 19. The LM command can only be issued when all
banks are idle, and a subsequent executable command cannot be issued until
met.
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA1–BA0 inputs selects the bank, and the address
provided on inputs (A13–A0 for x4 and x8, and A12–A0 for x16) selects the row. This row
remains active (or open) for accesses until a PRECHARGE command is issued to that
bank. A PRECHARGE command must be issued before opening a different row in the
same bank.
Before any READ or WRITE commands can be issued to a bank within the DDR2
SDRAM, a row in that bank must be opened (activated), even when additive latency is
used. This is accomplished via the ACTIVE command, which selects both the bank and
the row to be activated, as shown in Figure 15 on page 35.
After a row is opened with an ACTIVE command, a READ or WRITE command may be
issued to that row subject to the
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. The same procedure is used to convert other specification limits from time
units to clock cycles. For example, a
clock (
page 37, which covers any case where 5 <
case for
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been closed (precharged). The minimum time interval
between successive ACTIVE commands to the same bank is defined by
t
CK = 3.75ns) results in 5.3 clocks, rounded up to 6. This is reflected in Figure 17 on
t
RRD where 2 <
t
RRD (MIN) /
34
t
RCD specification.
t
RCD (MIN) specification of 20ns with a 266 MHz
t
CK ≤ 3.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCD (MIN) /
DESELECT, NOP, and LM Commands
512Mb: x4, x8, x16 DDR2 SDRAM
t
RCD (MIN) should be divided by
t
CK ≤ 6. Figure 17 also shows the
©2004 Micron Technology, Inc. All rights reserved.
t
RC.
t
MRD is