PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 815
PNX1700EH,557
Manufacturer Part Number
PNX1700EH,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1700EH557.pdf
(832 pages)
Specifications of PNX1700EH,557
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Philips Semiconductors
Volume 1 of 1
Table 5: DTL Interface Rules
PNX17XX_SER_1
Preliminary data sheet
Module
Item Unit
Size
8 bits
16 bits
32 bits
System
Endian Mode
either
either
either
6.2.1 DTL Data Ordering Rules
6.2 DMA Across a DTL Interface
Two standard solutions are provided to interface the DTL to the PMAN MTL network
buses:
Note that the connection from the 32-bit DTL interface to the MTL Bus uses swapping
only if the 32-bit DTL interface is not address invariant.
The following subsections show how unit data of different lengths travels across the
three key interfaces: the 32-bit DTL interface, the DCS Network and the MTL Memory
Bus.
Modules that interface to the DTL bus can deal with data on the bus in two ways:
Data is transferred across the DTL Interface by the following rules:
Modules dealing with 8, 16 or 32-bit units must place bytes on the DTL interface given
in
views based on the cmd_data_size .
DTL_D[31:24]
item #4 with
address a+3
item #2 with address a+2
bits 15..8
item with address a
bits 31..24
•
•
•
•
•
•
Table
The “PMAN Buffer” connects the 32-bit DTL interface to the MTL-Bus.
The “packer Lego” and “DMA Buffering” map the 32-bit DTL interface to the 64-bit
MTL Memory Bus.
Data can be put on the bus in their natural form (without flipping them for endian
mode but indicating the size of the data with cmd_data_size ). In this case, the
module is not aware of the SYS_ENDIAN bit in the system. The module follows
DTL data ordering rules.
Modules can put the data on the bus in the address invariant mode (Note: This is
also the 8-bit mode). In this mode, the module uses the SYS_ENDIAN bit to flip
the data appropriately depending on the size of the data and the system endian
mode.
The value of cmd_data_size indicates the width of the data item(s) as 8 *
2
16-bit data, cmd_data_size is 0x1, etc.
In all cases, the data item (e.g. Byte) that corresponds to the lowest address is
transferred on the low order data bits of the DTL rd_data or wr_data
cmd_data_size
7. The Endian Swap Units then convert the data into true address invariant
bits. For example, with 8-bit data, cmd_data_size is set to 0x0, for
Rev. 1 — 17 March 2006
DTL_D[23:16]
item #3 with
address a+2
bits 7..0
bits 23..16
DTL_D[15:8]
item #2 with
address a+1
item #1 with address a
bits 15..8
bits 15..8
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 29: Endian Mode
DTL_D[7:0]
item #1 with
address a
bits 7..0
bits 7..0
29-11
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