PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 157
PNX1700EH,557
Manufacturer Part Number
PNX1700EH,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1700EH557.pdf
(832 pages)
Specifications of PNX1700EH,557
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Philips Semiconductors
Volume 1 of 1
Table 1: PNX17xx Series Module and Bus Clocks
PNX17XX_SER_1
Preliminary data sheet
Bus or
Module
QVCP
VIP
VLD
AI
AO
Signal Name
clk_qvcp_out
clk_qvcp_pix
clk_qvcp_proc
clk_lcd_tstamp
clk_vip
clk_vld
ai_osclk
ai_sck
ao_osclk
ao_sck
Description
VDO_CLK1
External pixel clock
internal pixel clock
processing layer
clock
LCD timestamp
VDI_CLK1
External pixel clock
MPEG-2 Variable
Length Decoder
AO_OSCLK
External
Oversampling clock
AI_OSCLK
External
Oversampling clock
Frequencies
Up to 148 MHz
Typical values:
Up to 148 MHz
27 MHz
up to 81 MHz
up to 50 MHz
up to 25 MHz
up to 50 MHz
up to 25 MHz
Rev. 1 — 17 March 2006
• 27 MHz
• 54 MHz
• 65 MHz
• 144 MHz
• 133 MHz
• 157 MHz
• 96 MHz
• 86 MHz
• 78 MHz
• 58 MHz
• 39 MHz
• 33 MHz
• 17 MHz
• 144 MHz
• 133 MHz
• 108 MHz
• 96 MHz
• 86 MHz
• 78 MHz
• 72 MHz
• 66 MHz
MMIO Clock Module Control
Register(s)
PLL1_CTL
DDS1_CTL
CLK_QVCP_CTL
CLK_QVCP_PIX_CTL
CLK_QVCP_PROC_CTL
up to 157 MHz.
N/A
DDS7_CTL
CLK_VIP_CTL
CLK_VLD_CTL
DDS4_CTL
AI_OSCLK_CTL
AI_SCK_CTL
AO_OSCLK_CTL
AO_SCK_CTL
• PLL1_CTL and
• or DDS3_CTL
DDS1_CTL
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Standard
Clock Source
Smoothing
DDS1/PLL1
combination
INTERNAL
1.728 GHz DIVIDERS
EXTERNAL
1.728 GHz DIVIDERS
DDS4
EXTERNAL or
INTERNAL
DDS3
EXTERNAL or
INTERNAL
5-6
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