PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 64

• Manufacturer Part Number: PNX1700EH,557
• Manufacturer: NXP Semiconductors

Specifications of PNX1700EH,557

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Volume 1 of 1
Table 33: QVCP, LCD and FGPO Timing With External Clock Generation
Table 34: VIP and FGPI Timing
PNX17XX_SER_1
Preliminary data sheet
Symbol
F
F
T
T
T
Symbol
F
F
T
T
QVCP
FGPO
CLK-DV
SU-CLK
H-CLK
VIP
FGPI
SU-CLK
H-CLK
Parameter
VDO_CLK1 frequency
VDO_CLK2 frequency
Clock to VDO_D[34:0] and VDO_AUX
Input setup time
Input hold time
Parameter
VDI_CLK1 frequency
VDI_CLK2 frequency
Input setup time
Input hold time
7.5 VIP and FGPI Interfaces
[33-1]
[33-2]
[33-3]
[33-4]
[33-5]
[34-1]
[34-2]
[34-3]
Figure 13: QVCP and FGPO I/O Timing
See timing measurement conditions
Timing applies when the data is output on a positive or a negative edge in double edge clock
mode, see
3. If the VDO_CLK[1,2] is inverted internally then the timing applies to the negative edge.
Timing applies for VDO_D[29], FGPO_REC_SYNC and FGPO_BUF_SYNC. VDO_D[29]
and FGPO_BUF_SYNC. These inputs are assumed asynchronous.
Maximum frequency may get reduced by the wide spread of propagation delay depending
on the application needs, i.e. input setup/hold time requirements of the receiving device.
Notes:
1. Timing applies whether the clock is external or internal.
2. Timing applies whether the data is output on a positive or a negative edge.
Table 1 on page
Rev. 1 — 17 March 2006
FGPO_REC_SYNC
FGPO_BUF_SYNC
FGPO_REC_SYNC
FGPO_BUF_SYNC
VDO_D[34:0]
VDO_D[29]
VDO_CLK
VDO_CLK
3-6.
Figure
Min
3.5
4
4
Min
3
2
13.
T
SU-CLK
Chapter 1: Integrated Circuit Data
Max
81
81
Max
81
100
8
valid
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
T
T
CLK-DV
H-CLK
valid
Units
MHz
MHz
ns
ns
ns
Units
MHz
MHz
ns
ns
Notes
5
5
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
Notes
1, 2, 3
1, 2, 3
1-37