PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 809

• Manufacturer Part Number: PNX1700EH,557
• Manufacturer: NXP Semiconductors

Specifications of PNX1700EH,557

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Volume 1 of 1
Table 2: Register Result of an (Unsigned) Load Instruction
PNX17XX_SER_1
Preliminary data sheet
Memory Content
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
The TM5250 CPU on the PNX17xx Series both support 8, 16 and 32-bit data types
and a memory system that is byte addressable. The CPU support a big-endian and
little-endian mode of operation. The effect of a CPU store instruction on memory is
defined in
quantity contained in the 16 lsbits of the CPU register. And the memory locations
affected are “a” and “a+1.” But which byte goes where is dependent upon endian
mode.
Table 1: Memory Result of a Store to Address ‘a’ Instruction
The effect of a CPU load instruction on a register is defined for unsigned and signed
loads in
In the case of an unsigned load, higher order bits are filled with zeroes. In the case of
a signed load, higher order bits are filled with the sign bit of the data item loaded.
Endian
Mode
little
little
little
big
big
big
Figure 3:
Table 2
R13
Content
0x04050607 8 bits
0x04050607 16 bits
0x04050607 32 bits
0x04050607 8 bits
0x04050607 16 bits
0x04050607 32 bits
Table
Little-Endian Layout of DMA_Descriptor
and
1. As an example, a 16-bit store operation always stores the 16-bit
Rev. 1 — 17 March 2006
Table
Data
Size
Word 2
A
3. Note that a load always sets all bits of the CPU register.
Result of Store
m[a] = 0x07
m[a] = 0x07; m[a+1] = 0x06
m[a] = 0x07; m[a+1] = 0x06; m[a+2] = 0x05; m[a+3] = 0x04
m[a] = 0x07
m[a] = 0x06; m[a+1] = 0x07
m[a] = 0x04; m[a+1] = 0x05; m[a+2] = 0x06; m[a+3] = 0x07
Endian
Mode
little
little
little
big
big
big
4
size
Data Size
8 bits
16 bits
32 bits
8 bits
16 bits
32 bits
(R13, Address a)
L
Word 1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
2
PNX17xx Series
Chapter 29: Endian Mode
Register Value Result of
Load
0x000000AA
0x0000BBAA
0xDDCCBBAA
0x000000AA
0x0000AABB
0xAABBCCDD
F
size
1
(Address a)
C
0
29-5