PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 421

• Manufacturer Part Number: PNX1700EH,557
• Manufacturer: NXP Semiconductors

Specifications of PNX1700EH,557

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Volume 1 of 1
Table 20: QVCP 1 Registers
PNX17XX_SER_1
Preliminary data sheet
Bit
11
10
9
8:6
5:3
2:0
Offset 0x10 E2BC
31:14
13
12
11:10
9
Symbol
PF_U2C
PF_M2C
PF_L2C
Unused
PF_OFFSET2
PF_OFFSET1
Unused
PF_ENDIAN
Unused
PF_PIX_MODE
Unused
Formats
…Continued
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
-
0
0
-
0
0
-
Value
Rev. 1 — 17 March 2006
Description
Controls upper channel format within layer
The conversion takes place after the color key unit before the
undither unit.
Controls middle channel format within layer
The conversion takes place after the color key unit before the
undither unit.
Controls lower channel format within layer
The conversion takes place after the color key unit before the
undither unit
Defines pixel offset (in bytes) within a multi-pixel 64-bit word for
channel 2 for semi-planar and planar modes.
The number will be truncated to the closest even number for
channel 2
Defines pixel offset (in bytes) within a multi-pixel 64-bit word.
Input format endian mode
Not available when PF_10B_MODE is on.
Pixel key output modes
Mode 11 is not available when PF_10B_MODE is on.
0 = data untouched
1 = data conversion two’s compliment <-> binary offset
0 = data untouched
1 = data conversion two’s compliment <-> binary offset
0 = data untouched
1 = data conversion two’s compliment <-> binary offset
0, 2 or 4 for 10-bit YUV 4:2:2 semi-planar format
0 to 7 for 8-bit YUV 4:2:2 semi-planar format
0, 2 or 4 for 10-bit YUV 4:2:2 semi-planar format
0 or 4 for 10-bit (20 bpp) packed YUV 4:2:2 format
0, 2, 4 or 6 for 8-bit (16 bpp) packed YUV 4:2:2 or 16-bit varible
format
0 or 4 for 32-bit varible format
0 to 7 for all the other formats
0: Same as system endian mode
1: Opposite of system endian mode
00: Both keys ‘0’
01: Bits [1:0] of V/B output
10: Key 2 Bit [7] of alpha output
11: Key 2 AND of pixel key and alpha is not zero
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 11: QVCP
11-64