PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 755
PNX1700EH,557
Manufacturer Part Number
PNX1700EH,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1700EH557.pdf
(832 pages)
Specifications of PNX1700EH,557
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
3.1.1 Handshaking and Communication Protocol
The following describes the mechanism for transferring data via JTAG.
Transfer from Debug Front-End to Debug Monitor
The debugger front-end running on a host transfers data to a debug monitor via the
TM_DBG_DATA_IN register. It must poll the TM_DBG_CTRL2.ifull bit to check if the
TM_DBG_DATA_IN register can be written to. If the TM_DBG_CTRL2.ifull bit is clear,
the front-end may scan data into the TM_DBG_DATA_IFULL_IN register.
Note that data and control bits may be shifted in with SEL_IFULL_IN instruction and
the bit shifted into TM_DBG_CTRL2.ifull register must be 1. This action triggers an
interrupt. The debug monitor must copy the data from TM_DBG_DATA_IN register
into its private area when servicing the interrupt and then clear the
TM_DBG_CTRL2.ifull bit. This allows the JTAG interface module to write the next
piece of data to the TM_DBG_DATA_IN register.
Transfer from Monitor to Front-End
The monitor running on TM5250 must check if TM_DBG_CTRL1.ofull is clear and if
so, it can write data to TM_DBG_DATA_OUT. After that, the monitor must set the
TM_DBG_CTRL1.ofull bit. The debugger front-end polls the TM_DBG_CTRL1.ofull
bit. When set, it can scan out the TM_DBG_DATA_OUT register and clear the
TM_DBG_CTRL1.ofull bit. Since TM_DBG_DATA_OUT is read-only via JTAG, the
update action at the end of scan out has no effect on TM_DBG_DATA_ OUT. The
TM_DBG_CTRL1.ofull bit however, must be cleared by shifting in the value 1.
Controller States
In the power on reset state, TM_DBG_CTRL2.ifull, TM_DBG_CTRL1.ofull and
TM_DBG_CTRL1.sleepless bits are cleared.
Example of Data Transfer via JTAG
Scanning in a 5-bit instruction will take 12 TCK cycles from the Run-Test/Idle state:
Likewise, scanning in a 32-bit data register will take 38 TCK cycles, and transferring
an 8-bit TM_DBG_CTRL data register will take 14 TCK cycles from Idle state.
However, if a data transfer follows instruction transfer, then the transition to DR scan
stage can be done without going through Idle state, thereby saving 1 cycle.
•
•
•
•
•
4 cycles to reach Shift-IR state
5 cycles for actual shifting in
1 cycle to exit1-IR state
1 cycle to update-IR state,
1 cycle back to Run-Test/Idle state.
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 24: TM5250 Debug
PNX17xx Series
24-5
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