PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 372

• Manufacturer Part Number: PNX1700EH,557
• Manufacturer: NXP Semiconductors

Specifications of PNX1700EH,557

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
2.4.7 PLAN (Semi Planar DMA) Unit
2.5 Screen Timing Generator
This pool element contains one DMA channel which can be independently assigned
to any layer. By default, this DMA channels is assigned to the first layer. The DMA
channel is meant for fetching UV data in parallel to the fetching of Y-data by the DMA
unit that is already present inside each layer.
The Screen Timing Generator (STG) creates the required synchronization signals for
the monitor or other display devices. The screen timing generator usually operates as
the timing master in the system. However, it is also possible to synchronize the
operation of the screen timing generator to external events i.e., a vertical
synchronization signal. The screen timing generator also defines the active display
region. The coordinate system for the STG is (x, y), with (0, 0) referring to the top left
of the screen. The coordinate (Horizontal Total, Vertical Total) defines the bottom right
of the screen. Horizontal and vertical blanking intervals, synchronization signals, and
the visible display are within these boundaries.
Some of the control parameters that need to be set for the screen timing are:
The following rules apply to the register settings specifying the screen timing using
the above control parameters:
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HTOTAL = Total no. of pixels per line minus one
VTOTAL = Total no. of lines per field minus one
HSYNCS/E = Start/End pixel position of horizontal sync (Hsync)
VSYNCS/E = Start/End line position of vertical sync (Vsync)
HBLNKS/E = Start/End pixel position of horizontal blanking interval
VBLNKS/E = Start/End line position of vertical blanking interval
total number of pixel per line: HTOTAL + 1
total number of lines per field: VTOTAL + 1
0,1 < HBLNKS <=HTOTAL
0,1 < HSYNCS <= HTOTAL
0 < VBLNKS <= VTOTAL
0 < VSYNCS <= VTOTAL
Vsync - must be asserted or negated for at least one scanline
Hblank - must be asserted or negated for at least two clocks
Vblank - must be asserted or negated for at least two scanlines
Hsync - must be asserted or negated for at least one clock
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 11: QVCP
11-15