PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 495

• Manufacturer Part Number: PNX1700EH,557
• Manufacturer: NXP Semiconductors

Specifications of PNX1700EH,557

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
2.7.1 BUF1FULL and BUF2FULL Interrupts
2.7.2 THRESH1_REACHED and THRESH2_REACHED Interrupts
2.7.3 OVERRUN Interrupt
2.5 Records or Messages Per Buffer
2.6 Stride
2.7 Interrupt Events
The number of records or messages per buffer is set by FGPI_SIZE register.
If the number of records or messages per buffer is greater than one, the address
stride has to be programmed into the FGPI_STRIDE register.
Recording starts at a new location in the current buffer on each record or message
start event. After recording starts a new address is generated by adding the contents
of the FGPI_STRIDE register to the previous starting address.
Care must be taken that FGPI_STRIDE is greater than or equal to FGPI_REC_SIZE.
Add 4 if TSTAMP_SELECT is set. Add 4 if VAR_LENGTH is set.
The FGPI_IR_STATUS register contains buffer status and interrupt event status. To
generate an interrupt to the TriMedia processor the corresponding FGPI_IR_ENA bit
must be set. To clear an interrupt event (acknowledge the interrupt) a ‘1’ must be
written to the corresponding FGPI_IR_CLR bit. The FGPI_IR_SET register can be
used to generate software interrupts.
When the number of records or messages received and stored in a main memory
buffer equals the value in the FGPI_SIZE register an associated Buffer Full interrupt
will be generated.
Remark: Received records or messages ARE GUARANTEED to be in main memory
when the BUFnDONE interrupt is received.
When FGPI_NRECn (the number of records or messages stored in memory buffer n)
equals the contents of the FGPI_THRESHn register then the associated
THRESHn_REACHED bit will be set in the FGPI_IR_STATUS register.
The THRESHn_REACHED condition is ‘sticky’ and can only be cleared by software
writing a ‘1’ to the FGPI_IR_CLR.THRESHn_REACHED_ACK bit.
WARNING: Received records or messages ARE NOT GUARANTEED to be in main
memory when the THRESHn_REACHED interrupt is received. The only interrupt that
guarantees that the records or messages are in main memory are the BUFnDONE
interrupts.
If software fails to assign a new buffer (update FGPI_BASEn register) and perform an
interrupt acknowledge (clear BUFnFULL interrupt) before both buffers fill up, the
interrupt event FGPI_IR_STATUS.OVERRUN will be set and capture of samples will
stop.
This happens when the FGPI switches to a buffer for which:
Rev. 1 — 17 March 2006
Chapter 14: FGPI: Fast General Purpose Interface
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
14-8