PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 111

• Manufacturer Part Number: PNX1700EH,557
• Manufacturer: NXP Semiconductors

Specifications of PNX1700EH,557

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
2.1 The PCI View
Before going into the details of the three different views the following generic rules
should be noted:
These apertures need to be programmed at boot time or by the host before the
system can be operational. The internal boot scripts have pre-defined values for
these apertures (refer to
The PCI module provides three different apertures to the external PCI bus masters:
Any supported request on the PCI bus that falls outside of these three apertures is
discarded by the PCI module and therefore does not interfere with the PNX17xx
Series system.
In addition PCI transactions to the XIO aperture from external PCI agents are
discarded.
Figure 2
PNX17xx Series system. The apertures can be placed in any order with respect to
each other.
The aperture locations is programmed by the host CPU.
The aperture sizes can be programmed at boot time via some GPIO/BOOT_MODE[]
pins as defined in
CPU using PCI configuration cycles.
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The three views must be consistent. For example, it is not allowed to have a
different DRAM aperture location for the TM5250 CPU and the PCI module.
The apertures are “naturally aligned”. For example a 32-Megabyte aperture has a
starting address that is a multiple of 32 Megabytes.
Each aperture can be located anywhere in the 32-bit addressing space.
All the modules in the PNX17xx Series SOC sees the same memory map, i.e. an
address represents an unique location for all the modules.
the MMIO aperture, used to access all the internal PNX17xx Series registers.
See
the DRAM aperture, used to access to the main memory of PNX17xx Series.
the XIO aperture, used by TM5250 to access low speed slave devices like Flash
memories or IDE disk drives.
The MMIO aperture is starting at the address contained in the BASE_14 PCI
configuration space register.
The DRAM aperture is starting at the address contained in the BASE_10 PCI
configuration space register.
The XIO aperture is starting at the address contained in the BASE_18 PCI
configuration space register.
Section 11. on page 3-31
presents the memory map seen by the PCI module and the remaining of the
Chapter 6 Boot Module
Rev. 1 — 17 March 2006
Chapter 6 Boot
for offset allocation per module.
Module).
or they can be programmed by the host
Chapter 3: System On Chip Resources
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
3-2