PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 60

• Manufacturer Part Number: PNX1700EH,557
• Manufacturer: NXP Semiconductors

Specifications of PNX1700EH,557

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Volume 1 of 1
Table 28: Reset Timing
Table 29: DDR DRAM Interface Timing
PNX17XX_SER_1
Preliminary data sheet
Symbol
T
T
T
Symbol
F
T
T
T
T
T
oh-dq
LOWP
HOLD
LOWR
ddr
ddr
cs
pd-cmd
s-dq
Parameter
Reset active time after power and clock stable
Reset active after POR_IN_N is pulled high
Reset active time after power and clock stable
Parameter
MM_CLK and MM_CLK_N frequency
MM_CLK and MM_CLK_N period
MM_CLK and MM_CLK_N skew
Propagation delay for command signals
Setup time for MM_DQ and MM_DQM
(when writing to DDR SDRAM)
Output hold time for MM_DQ and MM_DQM
(when writing to DDR SDRAM)
7.1 Reset
7.2 DDR DRAM Interface
[28-1]
[28-2]
[28-3]
PNX1700 supports DDR200, DDR266, DDR400{A,B,C} DDR devices as defined in
the JEDEC STANDARD JESD79C, March 2003. Refer to
interface
Figure 9:
Notes:
1. Can be asserted and de-asserted asynchronously with respect to CLK.
2. If POR_IN_N and RESET_IN_N are asserted low then RESET_IN_N must stay low for at
least as long as POR_IN_N is asserted low.
for more details.
Reset Timing
Rev. 1 — 17 March 2006
POR_IN_N
RESET_IN_N
T
Min
83
5
1.4
- 0.12
0.12
LOWP
Min
100
0
100
T
LOWR
Chapter 1: Integrated Circuit Data
T
HOLD
Max
Section 4.
12
0.01
3.6
Max
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Section 10.3 DDR SDRAM
PNX17xx Series
Units
MHz
ns
ns
ns
T
T
ddr
ddr
Units
ns
s
s
Notes
i.e. up to
DDR400
1, 2, 3, 5
4, 5
4, 5
Notes
1
2
1
1-33