PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 63
PNX1700EH,557
Manufacturer Part Number
PNX1700EH,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1700EH557.pdf
(832 pages)
Specifications of PNX1700EH,557
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Philips Semiconductors
Volume 1 of 1
Table 31: QVCP, LCD and FGPO Timing With Internal Clock Generation
Table 32: QVCP, LCD and FGPO Timing With External Clock Generation
PNX17XX_SER_1
Preliminary data sheet
Symbol
F
F
T
T
T
Symbol
F
F
T
T
T
QVCP
FGPO
CLK-DV
SU-CLK
H-CLK
QVCP
FGPO
CLK-DV
SU-CLK
H-CLK
Parameter
VDO_CLK1 frequency
VDO_CLK2 frequency
Clock to VDO_D[34:0] and VDO_AUX
Input setup time
Input hold time
Parameter
VDO_CLK1 frequency
VDO_CLK2 frequency
Clock to VDO_D[34:0] and VDO_AUX
Input setup time
Input hold time
7.4 QVCP, LCD and FGPO Interfaces
[31-1]
[31-2]
[31-3]
[31-4]
[31-5]
[31-6]
Figure 12: QVCP and FGPO I/O Timing
See timing measurement conditions
Timing applies when the data is output on a positive or a negative edge in double edge clock
mode, see
If the VDO_CLK[1,2] is inverted internally then the timing applies to the negative edge.
Timing applies for VDO_D[29], FGPO_REC_SYNC and FGPO_BUF_SYNC. VDO_D[29]
and FGPO_BUF_SYNC. This inputs are assumed asynchronous.
In double edge clock mode, the maximum VDO_CLK1 frequency is lower than in single edge
clock mode. Refer to
The SAA7104H/5H input hold time specification for the data lines, PD[11:0], is actually 1.2
ns. The SAA7104H/5H input hold time specification for the xSVGC lines (SYNC signals)
remains 1.5 ns; therefore traces on the board should compensate for the missing 0.3 ns
delay.
Table 1 on page
Rev. 1 — 17 March 2006
FGPO_REC_SYNC
FGPO_BUF_SYNC
FGPO_REC_SYNC
FGPO_BUF_SYNC
VDO_D[34:0]
Section 4.
VDO_D[29]
VDO_CLK
VDO_CLK
3-6.
for differences in between the different devices.
Figure
Min
1.2
3
2
Min
3
4
4
13.
T
SU-CLK
Chapter 1: Integrated Circuit Data
Max
Section 4.
100
Max
81
81
3.8
11
valid
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
T
T
CLK-DV
H-CLK
valid
Units
MHz
MHz
ns
ns
ns
Units
MHz
MHz
ns
ns
ns
Notes
5
1, 2, 3, 6
1, 2, 3, 4
1, 2, 3, 4
Notes
5
5
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
1-36
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