PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 123

• Manufacturer Part Number: PNX1700EH,557
• Manufacturer: NXP Semiconductors

Specifications of PNX1700EH,557

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Volume 1 of 1
Table 5: Interrupt Source Assignments
PNX17XX_SER_1
Preliminary data sheet
SOURCE NAME
APPLICATION
DEBUGGER
RTOS
Reserved
DCS
MMI
Reserved
6.2 Timers
SOURCE
NUMBER
49
50
51
52...59
60
61
62...63
The TM5250 CPU contains eight programmable timer/counters, all with the same
function. The first seven (TIMER1, ..., TIMER7) are intended for general use. The
eight timer/counter (SYSTIMER) is reserved for use by the system software and
should not be used by applications.
Each timer/counter can be set to count one of the event types specified in
Note that source 3 to 6 are special TM5250 events used for program debug support
as well as cache performance monitoring. Full description can be found in [1]. For all
the other source signals, like the VDO_CLK1 pin, positive-going edges on the signal
are counted. Each timer increments its value until the programmed count is reached.
On the clock cycle when the timer reaches its programmed count value, an interrupt
is generated.
The timer interrupt source mode should be set as edge-sensitive as presented in
Table
Table 6: TM5250 Timer Source Selection
SOURCE NAME
TM5250 CLOCK
PRESCALE
Reserved
DATABREAK
INSTBREAK
CACHE1
CACHE2
CACHE3
CACHE4
VDI_CLK1
VDO_CLK1
AI_WS
AO_WS
5. No software interrupt acknowledge to the timer device is necessary.
INTERRUPT
OPERATING MODE
edge
edge
edge
n/a
level
level
n/a
Rev. 1 — 17 March 2006
SOURCE NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
SOURCE DESCRIPTION
(software) Application
(software) Debugger
(software) Real Time Operating System
Reserved for future devices
Internal DCS bus
Main Memory Interface, i.e. the DRAM controller
Reserved for future devices
Chapter 3: System On Chip Resources
SOURCE DESCRIPTION
The CPU clock
Pre-scaled CPU clock
Reserved for future devices
Data breakpoints
Instruction breakpoints
Cache event 1
Cache event 2
Cache event 3
Cache event 4
VIP clock pin
QVCP clock pin
AI Word Strobe pin
AO Word Strobe pin
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Table
6.
3-14