PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 810

• Manufacturer Part Number: PNX1700EH,557
• Manufacturer: NXP Semiconductors

Specifications of PNX1700EH,557

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Volume 1 of 1
Table 3: Register Result of a (Signed) Load Instruction
PNX17XX_SER_1
Preliminary data sheet
Memory Content
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
Figure 4:
int w = 0x04050607;
char *a = (char *)&w;
Memory Content Created by the C Program
3.2 Law 2: The “DMA Convention Rule”
An interesting example is the small C program below that determines whether the
program runs on a big-endian or little-endian mode machine.
The DMA convention rule says that “when a stream of items enters the system, items
should be placed in memory such that an item that arrived later has a higher address
value.” On output, a similar convention holds—items sent first are those with the
lowest addresses.
A variant of this rule relates to the storage of images. Pixels from left to right have
increasing addresses. Lines from top to bottom have increasing addresses.
This is a convention that keeps programmers sane. It may also be seen as arbitrary,
but obviously the best choice between two alternatives.
A more precise version of this rule is:
If item ’0’ of a DMA item stream is placed at address “A,” item “i” of a DMA stream
should be placed at byte address “A+i*s,” where “s” is the item size in bytes.
For an example of this rule, refer to
int w = 0x04050607;
char *a = (char *) &w;
if (*a == 0x04) printf("big-endian"); else printf("little-endian");
Big-Endian Mode Memory Content
a+0
04
a+1
05
31
CPU Register Content
04
Rev. 1 — 17 March 2006
a+2
06
05
a+3
07
06
Endian
Mode
little
little
little
big
big
big
Section 5.
a+3
04
07
Little-Endian Mode Memory Content
Data Size
8 bits
16 bits
32 bits
8 bits
16 bits
32 bits
0
a+2
05
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 29: Endian Mode
Register Value Result of
Load
0xFFFFFFAA
0xFFFFBBAA
0xDDCCBBAA
0xFFFFFFAA
0xFFFFAABB
0xAABBCCDD
a+1
06
size
(address a)
a+0
07
29-6