PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 145

• Manufacturer Part Number: PNX1700EH,557
• Manufacturer: NXP Semiconductors

Specifications of PNX1700EH,557

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
2.2.1 The Non Interrupt Mode
2.2 The watchdog Timer
The internal PNX17xx Series watchdog timer has two operating modes. Both modes
result in the assertion of the internal reset signals, peri_rst_n and sys_rst_out_n
signals based upon a time-out condition. The modes are referenced as the non
interrupt mode and the interrupt mode.
In this mode, the watchdog timer operates as a simple counter. The counter operates
with the DCS clock also called MMIO clock (clk_dtl_mmio).
By default, i.e. after a PNX17xx Series system reset, this watchdog counter is not
active. The activation is done by writing a value different than 0x0 to the
WATCHDOG_COUNT MMIO register. Upon that write, an internal counter of the
watchdog timer is reset to 0x0 and starts to count. If the internal counter reaches the
WATCHDOG_COUNT value then peri_rst_n and sys_rst_out_n internal reset signals
are asserted and the PNX17xx Series system is reset. The reset follows then the
regular software reset timing,
WATCHDOG_COUNT MMIO register before the internal counter reaches the
previous WATCHDOG_COUNT value then the internal reset signals are not
generated and the internal counter stops counting. Similarly if the CPU writes a value
different than 0x0 then the internal counter is reset to 0x0 and starts to count to the
new WATCHDOG_COUNT value.
This mode requires the CPU to come back in time to reset the internal counter on a
regular basis. TM5250 software may use some of its internal hardware timers [1] to
reset on time on the internal counter. The interrupt handler needs to first write a 0x0
value to the WATCHDOG_COUNT register then write a new count value.
The layout of the WATCHDOG_COUNT MMIO register is presented in
The following summarizes the sequence of operations
1. Start the internal counter by writing a nonzero value to the WATCHDOG_COUNT
2. A write with 0x0 value to the WATCHDOG_COUNT MMIO register will stop the
3. If step 2 does not occur before the count reaches the WATCHDOG_COUNT
MMIO register.
count. For continuous watchdog timer operation it is not required to write 0x0 first
but instead start back directly from step 1).
value the PNX17xx Series system reset is asserted.
Rev. 1 — 17 March 2006
Section
3.2. If the CPU writes a 0x0 value to the
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 4: Reset
Section
4..
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