PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 385

• Manufacturer Part Number: PNX1700EH,557
• Manufacturer: NXP Semiconductors

Specifications of PNX1700EH,557

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
Figure 9:
pool resource element, register not shadowed
regular function unit, registers not shadowed
pool resource element, register shadowed
regular function unit, register shadowed
Shadowing of Registers
Table 6
Table 6: Shadow Registers
Register
Dummy Pixel Count (0x10E[LAPT]14)
Layer Size (0x10E[LAPT]34)
Pixel Key AND Register (0x10E[LAPT]4C)
Output and Alpha manipulation (0x10E[LAPT]B8)
Formats (0x10E[LAPT]BC)
Variable Format register (0x10E[LAPT]C4)
Layer Source Address A (0x10E[LAPT]00)
Layer Pitch A (0x10E[LAPT]04)
Layer Source Width (0x10E[LAPT]08)
Layer Source Address B (0x10E[LAPT]0C)
Layer Pitch B (0x10E[LAPT]10)
Dummy Pixel Count (0x10E[LAPT]14)
Layer Start (0x10E[LAPT]30)
Layer Size (0x10E[LAPT]34)
Layer Pixel Processing (0x10E[LAPT]3C)
(except bits 0 and 1)
INTR (0x10E[LAPT]A8)
HSRU Phase (0x10E[LAPT]AC)
HSRU Delta Phase (0x10E[LAPT]B0)
Layer Size (final) (0x10E[LAPT]B4)
lists all shadowed registers (where LAPT stands for Layer APerTure):
STG_TIMING/VBI
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Used by
Pixel formatter
Pixel formatter
Pixel formatter
Pixel formatter
Pixel formatter
Pixel formatter
DMA
DMA
DMA
DMA
DMA
Pixel formatter
Layer Control
Layer Control
Pixel Formatter
Linear Interpolator
HSRU
HSRU
Layer Control / Scalers
PNX17xx Series
Chapter 11: QVCP
11-28