PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 405

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PNX1700EH,557

Manufacturer Part Number
PNX1700EH,557
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PNX1700EH,557

Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Philips Semiconductors
Volume 1 of 1
Table 20: QVCP 1 Registers
PNX17XX_SER_1
Preliminary data sheet
Bit
Offset 0x10 E020
31:30
29
28
27
26
25
24
23:21
20
19
18
17
16
15:12
Symbol
Unused
Interlaced
BlankPol
Unused
HSYNCPol
Unused
VSYNCPol
Unused
BlankCtl
Unused
HSYNCCtl
Unused
VSYNCCtl
Unused
CONTROL
…Continued
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
0
0
-
0
-
-
-
0
-
0
-
-
-
Value
Rev. 1 — 17 March 2006
Description
Interlaced mode bit
Field height = VTotal for odd fields.
Field height = VTotal+1 for even fields.
O_E flag = 0 for odd (bottom) fields
O_E flag =1 for even (top) fields
BLANK Polarity
HSYNC Polarity
VSYNC Polarity
Blank Control allows either normal blanking or forces blanking to
occur immediately.
HSYNC Control enables or disables the horizontal sync output of
the chip.
VSYNC Control enables or disables vertical sync output of the chip.
0 = Non-interlaced mode; VTotal=frame height.
1 = Interlaced mode
0 = Positive blank
1 = Negative blank
0 = Positive going
1 = Negative going
0 = Positive going
1 = Negative going
0 = Blank output is equivalent to BlankPol setting
1 = Normal Blank
0 = HSYNC output is equivalent to HSYNCPol setting
1 = Enable
0 = VSYNC output is equivalent to VSYNCPol setting
1 = Enable
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 11: QVCP
11-48

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