PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 132

• Manufacturer Part Number: PNX1700EH,557
• Manufacturer: NXP Semiconductors

Specifications of PNX1700EH,557

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Volume 1 of 1
Table 8: Global Registers
PNX17XX_SER_1
Preliminary data sheet
5
4:3
2:0
Bit
Symbol
VDO_MODE
Unused
VDO_MODE
…Continued
Acces
s
R/W
-
R/W
Value
0
-
0
Rev. 1 — 17 March 2006
Description
‘0’: No action
‘1’: When VDO_MODE[2:0] = 010, i.e. digital 16-bit YUV video:
QVCP_DATA[19:12] -> VDO_D[20:13] when VDO_CLK1=1
QVCP_DATA[9:2]
i.e. UV[7:0]
i.e. Y[7:0]
All the other VDO pins are mapped as described below for
VDO_MODE[2:0] = 010.
This mode is typically used to interface with Video Encoders like the
Philips SAA7104 that require the video data to be presented on both
edges of the pixel clock. This mode allows to transfer the 16-bit data
over an 8-bit interface, VDO_D[20:13].
Note: This mode requires a 50/50 duty cycle clock. This can be
achieved by programming the QVCP PLL at twice the speed and
divide it by 2 by setting the P divider to 1, or use a times 4 or 8 as
described in
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
TFT/QVCP mapping to VDO interface
000*: TFT LCD controller with 24- or 18-bit digital RGB/YUV
video
TFT_DATA[23:0]
TFT_VSYNC
TFT_HSYNC
TFT_DE
TFT_VDDON
TFT_BKLTON
TFT_CLK
In 18-bit mode
VDO_D[28:23]
VDO_D[20:15]
VDO_D[12:7]
In 24-bit mode
VDO_D[28:21]
VDO_D[20:13]
VDO_D[12:5]
001*: Digital ITU 656 YUV 8-/10-bit
QVCP_DATA[9:0] -> VDO_D[28:19]
QVCP_VSYNC
QVCP_HSYNC
QVCP_AUX1
QVCP_CLK
In 8-bit mode YUV[7:0] is mapped to VDO_D[28:21].
QVCP_AUX1 can be programmed to output, a CBLANK signal, a
Field indicator or a video/graphics detector.
Section PLL Settings page
-> VDO_CLK1
-> B[5:0] or V[5:0]
-> B[7:0] or V[5:0]
-> VDO_CLK1
-> VDO_D[29]
-> VDO_D[28:5]
-> VDO_D[30]
-> VDO_D[3]
-> R[5:0] or Y[5:0]
-> G[5:0] or U[5:0]
-> R[7:0] or Y[5:0]
-> G[7:0] or U[5:0]
-> VDO_D[31]
-> VDO_D[31]
-> VDO_D[4]
-> VDO_D[29]
-> VDO_D[30]
-> VDO_D[20:13] when VDO_CLK1=0
-> VDO_D[20:13] when VDO_CLK1=0
-> VDO_D[20:13] when VDO_CLK1=1
Chapter 3: System On Chip Resources
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
5-9.
3-23