PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 196

• Manufacturer Part Number: PNX1700EH,557
• Manufacturer: NXP Semiconductors

Specifications of PNX1700EH,557

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Volume 1 of 1
Table 11: CLOCK MODULE REGISTERS
PNX17XX_SER_1
Preliminary data sheet
Bit
3
2:1
0
Offset 0x04,7214
31:7
6
5:3
2:1
0
Offset 0x04,7300
31:4
3
2:1
0
Offset 0x04,7304
Symbol
vip_output_enable_n
sel_clk_vip
en_clk_vip
Reserved
turn_off_ack
sel_clk_vld_src
sel_clk_vld
en_clk_vld
Reserved
turn_off_ack
sel_ai_osclk
en_ai_osclk
CLK_VLD_CTL
AI_OSCLK_CTL
CLK_AI_SCK_CTL
Acces
s
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R
R/W
R/W
…Continued
Value
1
00
1
-
0
000
00
1
-
0
00
1
Rev. 1 — 17 March 2006
Description
VIP output enable
0: output, the clock is generated internally
1: input, the clock is provided by an external source unless
sel_clk_vip is 00 then it is still the xtal clock.
00: clk_vip = 27 MHz xtal_clk (overrides vip_output_enable_n).
The following is only valid when vip_output_enable_n is 0.
01: clk_vip = DDS7
10: clk_vip = DDS7
11: clk_vip = XIO_D[11]
1: enable clk_vip
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
000: clk_vld_src = clk_144
001: clk_vld_src = clk_123
010: clk_vld_src = clk_108
011: clk_vld_src = clk_96
100: clk_vld_src = clk_86
101: clk_vld_src = clk_78
110: clk_vld_src = clk_72
111: clk_vld_src = clk_66
00: clk_vld = 27 MHz xtal_clk
01: clk_vld = clk_vld_src
10: clk_vld = 27 MHz xtal_clk
11: clk_vld = XIO_D[12]
1: enable clk_vld
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
00: ai_osclk = 27 MHz xtal_clk
01: ai_osclk = DDS4
10: ai_osclk = 27 MHz xtal_clk
11: ai_osclk = XIO_D[13]
1: enable clk_ai_osclk
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
5-45