PNX1700EH,557 NXP Semiconductors, PNX1700EH,557 Datasheet - Page 198
PNX1700EH,557
Manufacturer Part Number
PNX1700EH,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1700EH557.pdf
(832 pages)
Specifications of PNX1700EH,557
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Philips Semiconductors
Volume 1 of 1
Table 11: CLOCK MODULE REGISTERS
PNX17XX_SER_1
Preliminary data sheet
Bit
4
3
2:1
0
Offset 0x04,7318-0x04,73FCReserved
General Purpose
Offset 0x04,7400
31:4
3
2:1
0
Offset 0x04,7404
31:4
3
2:1
0
Offset 0x04,7408
31:4
3
Symbol
turn_off_ack
sel_spdi_clk_src
sel_spdi_clk
en_clk_spdi
Reserved
turn_off_ack
sel_clk_gpio_q4_ctl
en_clk_gpio_q4_ctl
Reserved
turn_off_ack
sel_clk_gpio_q5_ctl
en_clk_gpio_q5_ctl
Reserved
turn_off_ack
CLK_GPIO_Q4_CTL
CLK_GPIO_Q5_CTL
CLK_GPIO_Q6_12_CTL
Acces
s
R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R
…Continued
Value
0
0
00
1
-
0
00
1
-
0
00
1
-
0
Rev. 1 — 17 March 2006
Description
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
0: clk_spdi_src = clk_144
1: clk_spdi_src = clk_72
00: clk_spdi = 27 MHz xtal_clk
01: clk_spdi = clk_spdi_src
10: clk_spdi = UNDEF
11: clk_spdi = LAN_TXD[0]
1: enable clk_spdi
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
00: clk_gpio_q4_ctl = 27 MHz xtal_clk
01: clk_gpio_q4_ctl = DDS8
10: clk_gpio_q4_ctl = 27 MHz xtal_clk
11: clk_gpio_q4_ctl = LAN_TXD[1]
1: enable clk_gpio_q4_ctl
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
00: clk_gpio_q5_ctl = 27 MHz xtal_clk
01: clk_gpio_q5_ctl = DDS7
10: clk_gpio_q5_ctl = 27 MHz xtal_clk
11: clk_gpio_q5_ctl = LAN_TXD[2]
1: enable clk_gpio_q5_ctl
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
5-47
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