MC9S08SH4CTG Freescale, MC9S08SH4CTG Datasheet - Page 81

• Manufacturer Part Number: MC9S08SH4CTG
• Manufacturer: Freescale

Specifications of MC9S08SH4CTG

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 256Byte
• # I/os (max): 13
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 4KB
• Lead Free Status / RoHS Status: Compliant

1
1
2
6.6.1.2
6.6.1.3
Freescale Semiconductor
PTADD[5:0]
PTAPE[5:0]
V
Reset:
PTADD4 has no effect on the output-only PTA4 pin.
Reset:
PTAPE5 can be used to pullup PTA5 when configured as open drain output pin, however pullup will not pull pin all the way to
PTAPE4 has no effect on the output-only PTA4 pin.
DD
Field
Field
5:0
. An external pullup should be used if applications requires PTA5 to be driven to V
5:0
W
W
R
R
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
Internal Pull Enable for Port A Bits — Each of these control bits determines if the internal pull-up or pull-down
device is enabled for the associated PTA pin. For port A pins (except for PTA5) that are configured as outputs,
these bits have no effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port A bit n.
1 Internal pull-up/pull-down device enabled for port A bit n.
Port A Data Direction Register (PTADD)
0
0
Port A Pull Enable Register (PTAPE)
0
0
7
7
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.
Figure 6-5. Internal Pull Enable for Port A Register (PTAPE)
0
0
0
0
6
6
Figure 6-4. Port A Data Direction Register (PTADD)
Table 6-3. PTADD Register Field Descriptions
Table 6-4. PTAPE Register Field Descriptions
MC9S08SH8 MCU Series Data Sheet, Rev. 3
PTAPE5
PTADD5
0
0
5
5
1
PTADD4
PTAPE4
NOTE
0
0
4
4
Description
Description
2
1
PTADD3
PTAPE3
3
0
3
0
PTADD2
PTAPE2
DD
Chapter 6 Parallel Input/Output Control
.
0
0
2
2
PTADD1
PTAPE1
0
0
1
1
PTADD0
PTAPE0
0
0
0
0
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