MC9S08SH4CTG Freescale, MC9S08SH4CTG Datasheet - Page 309

• Manufacturer Part Number: MC9S08SH4CTG
• Manufacturer: Freescale

Specifications of MC9S08SH4CTG

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 256Byte
• # I/os (max): 13
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 4KB
• Lead Free Status / RoHS Status: Compliant

A.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1
Freescale Semiconductor
1
2
3
4
Typical values are based on characterization data at V
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
When any reset is initiated, internal circuitry drives the reset pin low for about 66 cycles of t
frequency changes to the untrimmed DCO frequency (f
to 0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets trim stays at the pre-reset value.
Timing is shown with respect to 20% V
Nu
m
1
2
3
4
8
9
D
D
D
D
D
C
C
Control Timing
Bus frequency (t
Internal low power oscillator period
External reset pulse width
Reset low drive
Pin interrupt pulse width
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Asynchronous path
Synchronous path
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
Slew rate control enabled (PTxSE = 1)
Slew rate control disabled (PTxSE = 0)
RESET PIN
3
cyc
= 1/f
5
2
Rating
Bus
MC9S08SH8 MCU Series Data Sheet, Rev. 3
DD
2
)
and 80% V
Table A-13. Control Timing
Figure A-10. Reset Timing
DD
DD
reset
levels. Temperature range –40°C to 125°C.
4
= 5.0V, 25°C unless otherwise stated.
6
= (f
dco_ut
t
extrst
)/4) because TRIM is reset to 0x80 and FTRIM is reset
t
t
t
Symbol
ILIH,
Rise
Rise
t
t
t
rstdrv
f
extrst
LPO
Bus
, t
, t
t
IHIL
Fall
Fall
1.5 x t
66 x t
800
100
100
Min
dc
—
—
—
—
cyc
Appendix A Electrical Characteristics
cyc
cyc
. After POR reset the bus clock
Typ
40
75
11
35
—
—
1
1500
Max
20
—
—
—
—
—
—
—
MHz
Unit
μs
ns
ns
ns
ns
ns
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