MC9S08SH4CTG Freescale, MC9S08SH4CTG Datasheet - Page 65

• Manufacturer Part Number: MC9S08SH4CTG
• Manufacturer: Freescale

Specifications of MC9S08SH4CTG

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 256Byte
• # I/os (max): 13
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 4KB
• Lead Free Status / RoHS Status: Compliant

5.6
The MC9S08SH8 includes a system to protect against low voltage conditions in order to protect memory
contents and control MCU system states during supply voltage variations. The system is comprised of a
power-on reset (POR) circuit and a LVD circuit with trip voltages for warning and detection. The LVD
circuit is enabled when LVDE in SPMSC1 is set to 1. The LVD is disabled upon entering any of the stop
modes unless LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, then the MCU cannot enter
stop2, and the current consumption in stop3 with the LVD enabled will be higher.
5.6.1
When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset
rearm voltage level, V
LVD circuit will hold the MCU in reset until the supply has risen above the low voltage detection low
threshold, V
5.6.2
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. The low voltage detection threshold is determined by the LVDV bit. After an LVD reset has
occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the low
voltage detection threshold. The LVD bit in the SRS register is set following either an LVD reset or POR.
5.6.3
The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is
approaching the low voltage condition. When a low voltage warning condition is detected and is
configured for interrupt operation (LVWIE set to 1), LVWF in SPMSC1 will be set and an LVW interrupt
request will occur.
5.7
One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to
assignments for all registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, “Modes of
Freescale Semiconductor
Table 4-2
Low-Voltage Detect (LVD) System
Reset, Interrupt, and System Control Registers and Control Bits
Power-On Reset Operation
Low-Voltage Detection (LVD) Reset Operation
Low-Voltage Warning (LVW) Interrupt Operation
LVDL
. Both the POR bit and the LVD bit in SRS are set following a POR.
and
POR
Operation.”
Table 4-3
, the POR circuit will cause a reset condition. As the supply voltage rises, the
in
MC9S08SH8 MCU Series Data Sheet, Rev. 3
Chapter 4,
“Memory,” of this data sheet for the absolute address
Chapter 5 Resets, Interrupts, and General System Control
65