ATA6613P-PLPW Atmel, ATA6613P-PLPW Datasheet - Page 54

MCU W/LIN TXRX REG WTCHDG 48-QFN

ATA6613P-PLPW

Manufacturer Part Number
ATA6613P-PLPW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet

Specifications of ATA6613P-PLPW

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
54
Atmel ATA6612/ATA6613
Table 6-6.
Notes:
The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in
Table
Table 6-7.
Notes:
Oscillator Source/
Power Conditions
Ceramic resonator, fast
rising power
Ceramic resonator,
slowly rising power
Ceramic resonator, BOD
enabled
Ceramic resonator, fast
rising power
Ceramic resonator,
slowly rising power
Crystal Oscillator, BOD
enabled
Crystal Oscillator, fast
rising power
Crystal Oscillator, slowly
rising power
Frequency Range
6-7.
1. The frequency ranges are preliminary values. Actual values are TBD.
2. This option should not be used with crystals, only with ceramic resonators.
3. If 8MHz frequency exceeds the specification of the device (depends on V
1. These options should only be used when not operating close to the maximum frequency of
2. These options are intended for use with ceramic resonators and will ensure frequency stabil-
Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured
that the resulting divided clock meets the frequency specification of the device.
the device, and only if frequency stability at start-up is not important for the application.
These options are not suitable for crystals.
ity at start-up. They can also be used with crystals when not operating close to the maximum
frequency of the device, and if frequency stability at start-up is not important for the
application.
8.0 - 16.0
0.4 - 0.9
0.9 - 3.0
3.0 - 8.0
Low Power Crystal Oscillator Operating Modes
Start-up Times for the Low Power Crystal Oscillator Clock Selection
(1)
(MHz)
Start-up Time from
Power-down and
Power-save
16KCK
16KCK
16KCK
258CK
258CK
1KCK
1KCK
1KCK
CKSEL3..1
100
111
101
110
(2)
Additional Delay
Recommended Range for Capacitors C1
14CK + 4.1ms
14CK + 4.1ms
14CK + 65ms
14CK + 65ms
14CK + 4.1ms
14CK + 65ms
(V
from Reset
CC
14CK
14CK
= 5.0V)
(3)
(2)
(1)
(2)
(1)
(2)
and C2 (pF)
12 - 22
12 - 22
12 - 22
CKSEL0
0
0
0
0
1
1
1
1
CC
9111H–AUTO–01/11
), the CKDIV8
SUT1..0
00
01
10
11
00
01
10
11

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