ATA6613P-PLPW Atmel, ATA6613P-PLPW Datasheet - Page 212

• Manufacturer Part Number: ATA6613P-PLPW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLPW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.17.8.1
6.17.9
6.17.9.1
212
Atmel ATA6612/ATA6613
USART Register Description
Using MPCMn
USART I/O Data Register n– UDRn
For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZn = 7).
The ninth bit (TXB8n) must be set when an address frame (TXB8n = 1) or cleared when a data
frame (TXB = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit
character frame format.
The following procedure should be used to exchange data in Multi-processor Communication
mode:
Using any of the 5- to 8-bit character frame formats is possible, but impractical since the
Receiver must change between using n and n+1 character frame formats. This makes
full-duplex operation difficult since the Transmitter and Receiver uses the same character size
setting. If 5- to 8-bit character frames are used, the Transmitter must be set to use two stop bit
(USBSn = 1) since the first stop bit is used for indicating the frame type.
Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The
MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be
cleared when using SBI or CBI instructions.
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share
the same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer
Register (TXB) will be the destination for data written to the UDRn Register location. Reading
the UDRn Register location will return the contents of the Receive Data Buffer Register (RXB).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set
to zero by the Receiver.
1. All Slave MCUs are in Multi-processor Communication mode (MPCMn in
2. The Master MCU sends an address frame, and all slaves receive and read this frame.
3. Each Slave MCU reads the UDRn Register and determines if it has been selected. If
4. The addressed MCU will receive all data frames until a new address frame is
5. When the last data frame is received by the addressed MCU, the addressed MCU
Initial Value
Read/Write
Bit
UCSRnA is set).
In the Slave MCUs, the RXCn Flag in UCSRnA will be set as normal.
so, it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte
and keeps the MPCMn setting.
received. The other Slave MCUs, which still have the MPCMn bit set, will ignore the
data frames.
sets the MPCMn bit and waits for a new address frame from master. The process
then repeats from 2.
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
RXB[7:0]
TXB[7:0]
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
9111H–AUTO–01/11
UDRn (Read)
UDRn (Write)