ATA6613P-PLPW Atmel, ATA6613P-PLPW Datasheet - Page 149

• Manufacturer Part Number: ATA6613P-PLPW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLPW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.14.8.4
9111H–AUTO–01/11
Phase Correct PWM Mode
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by
setting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). This applies
only if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will
have a maximum frequency of f
ture is similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output
Compare unit is enabled in the fast PWM mode.
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a
dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and
then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare
(OC1x) is cleared on the compare match between TCNT1 and OCR1x while upcounting, and
set on the compare match while downcounting. In inverting Output Compare mode, the opera-
tion is inverted. The dual-slope operation has lower maximum operation frequency than single
slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these
modes are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or
defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A
set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM
resolution in bits can be calculated by using the following equation:
In phase correct PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1
(WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the
TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer
clock cycle. The timing diagram for the phase correct PWM mode is shown on
page
TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the
dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The
small horizontal line marks on the TCNT1 slopes represent compare matches between
OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs.
R
PCPWM
150. The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define
=
log
---------------------------------- -
log
TOP
2
+
1
OC
1
A
= f
clk_I/O
/2 when OCR1A is set to zero (0x0000). This fea-
Atmel ATA6612/ATA6613
Figure 6-47 on
149