ATA6613P-PLPW Atmel, ATA6613P-PLPW Datasheet - Page 239

• Manufacturer Part Number: ATA6613P-PLPW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLPW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9111H–AUTO–01/11
• Bit 6 – TWEA: TWI Enable Acknowledge Bit
• Bit 5 – TWSTA: TWI START Condition Bit
• Bit 4 – TWSTO: TWI STOP Condition Bit
• Bit 3 – TWWC: TWI Write Collision Flag
• Bit 2 – TWEN: TWI Enable Bit
• Bit 1 – Res: Reserved Bit
• Bit 0 – TWIE: TWI Interrupt Enable
While the TWINT Flag is set, the SCL low period is stretched. The TWINT Flag must be
cleared by software by writing a logic one to it. Note that this flag is not automatically
cleared by hardware when executing the interrupt routine. Also note that clearing this flag
starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI
Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clear-
ing this flag.
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written
to one, the ACK pulse is generated on the TWI bus if the following conditions are met:
The device’s own slave address has been received.
A general call has been received, while the TWGCE bit in the TWAR is set.
A data byte has been received in Master Receiver or Slave Receiver mode.
By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire
Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit
to one again.
The application writes the TWSTA bit to one when it desires to become a Master on the
2-wire Serial Bus. The TWI hardware checks if the bus is available, and generates a
START condition on the bus if it is free. However, if the bus is not free, the TWI waits until
a STOP condition is detected, and then generates a new START condition to claim the
bus Master status. TWSTA must be cleared by software when the START condition has
been transmitted.
Writing the TWSTO bit to one in Master mode will generate a STOP condition on the
2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is
cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover from
an error condition. This will not generate a STOP condition, but the TWI returns to a
well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high
impedance state.
The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when
TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high.
The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is
written to one, the TWI takes control over the I/O pins connected to the SCL and SDA
pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is
switched off and all TWI transmissions are terminated, regardless of any ongoing
operation.
This bit is a reserved bit and will always read as zero.
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will
be activated for as long as the TWINT Flag is high.
Atmel ATA6612/ATA6613
239