ATA6613P-PLPW Atmel, ATA6613P-PLPW Datasheet - Page 172

• Manufacturer Part Number: ATA6613P-PLPW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLPW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.15.7
172
Atmel ATA6612/ATA6613
Timer/Counter Timing Diagrams
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF
when WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (see
OC2x value will only be visible on the port pin if the data direction for the port pin is set as out-
put. The PWM waveform is generated by clearing (or setting) the OC2x Register at the
compare match between OCR2x and TCNT2 when the counter increments, and setting (or
clearing) the OC2x Register at compare match between OCR2x and TCNT2 when the counter
decrements. The PWM frequency for the output when using phase correct PWM can be calcu-
lated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
even though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
The following figures show the Timer/Counter in synchronous mode, and the timer clock
(clk
replaced by the Timer/Counter Oscillator clock. The figures include information on when Inter-
rupt Flags are set.
figure shows the count sequence close to the MAX value in all modes other than phase correct
PWM mode.
Figure 6-60. Timer/Counter Timing Diagram, no Prescaling
f
OCnxPCPWM
• OCR2A changes its value from MAX, like in
• The timer starts counting from a value higher than the one in OCR2A, and for that reason
(clk
value is MAX the OCn pin value is the same as the result of a down-counting compare
match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to
the result of an up-counting Compare Match.
misses the Compare Match and hence the OCn change that would have happened on the
way up.
T2
TCNTn
TOVn
clk
) is therefore shown as a clock enable signal. In asynchronous mode, clk
I/O
clk
/1)
TN
I/O
=
-------------------- -
N
f
clk_I/O
Figure 6-60
510
MAX - 1
Figure 6-59 on page 171
contains timing data for basic Timer/Counter operation. The
MAX
Figure 6-59 on page
OCnx has a transition from high to low
Table 6-60 on page
BOTTOM
171. When the OCR2A
175). The actual
BOTTOM + 1
9111H–AUTO–01/11
I/O
should be