ATA6613P-PLPW Atmel, ATA6613P-PLPW Datasheet - Page 198
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6613P-PLPW
Manufacturer Part Number
ATA6613P-PLPW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6613P-PLPW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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6.17.3
198
Atmel ATA6612/ATA6613
Frame Formats
A serial frame is defined to be one character of data bits with synchronization bits (start and
stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combina-
tions of the following as valid frame formats:
A frame starts with the start bit followed by the least significant data bit. Then the next data
bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the
parity bit is inserted after the data bits, before the stop bits. When a complete frame is trans-
mitted, it can be directly followed by a new frame, or the communication line can be set to an
idle (high) state.
inside brackets are optional.
Figure 6-72. Frame Formats
The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in
UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that chang-
ing the setting of any of these bits will corrupt all ongoing communication for both the Receiver
and Transmitter.
The USART Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The
USART Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection
between one or two stop bits is done by the USART Stop Bit Select (USBSn) bit. The Receiver
ignores the second stop bit. An FE (Frame Error) will therefore only be detected in the cases
where the first stop bit is zero.
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
St
(n)
P
Sp
IDLE
(IDLE)
Figure 6-72
St
Start bit, always low.
Data bits (0 to 8).
Parity bit. Can be odd or even.
Stop bit, always high.
No transfers on the communication line (RxDn or TxDn). An IDLE line
must be high.
0
1
illustrates the possible combinations of the frame formats. Bits
2
3
4
FRAME
[5]
[6]
[7]
[8]
[P]
Sp1 [Sp2]
(St / IDLE)
9111H–AUTO–01/11
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