ATA6613P-PLPW Atmel, ATA6613P-PLPW Datasheet - Page 35

• Manufacturer Part Number: ATA6613P-PLPW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLPW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.4.3
6.4.4
9111H–AUTO–01/11
ALU – Arithmetic Logic Unit
Status Register
The high-performance AVR
pose working registers. Within a single clock cycle, arithmetic operations between general
purpose registers or between a register and an immediate are executed. The ALU operations
are divided into three main categories – arithmetic, logical, and bit-functions. Some implemen-
tations of the architecture also provide a powerful multiplier supporting both signed/unsigned
multiplication and fractional format. See the “Instruction Set” section for a detailed description.
The Status Register contains information about the result of the most recently executed arith-
metic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using
the dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and
restored when returning from an interrupt. This must be handled by software.
The AVR Status Register – SREG – is defined as:
Bit
Read/Write
Initial Value
• Bit 7 – I: Global Interrupt Enable
• Bit 6 – T: Bit Copy Storage
• Bit 5 – H: Half Carry Flag
• Bit 4 – S: Sign Bit, S = N
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual
interrupt enable control is then performed in separate control registers. If the Global Inter-
rupt Enable Register is cleared, none of the interrupts are enabled independent of the
individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has
occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can
also be set and cleared by the application with the SEI and CLI instructions, as described
in the instruction set reference.
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or
destination for the operated bit. A bit from a register in the Register File can be copied into
T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register
File by the BLD instruction.
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is
useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple-
ment Overflow Flag V. See the “Instruction Set Description” for detailed information.
R/W
7
0
I
R/W
6
T
0
®
ALU operates in direct connection with all the 32 general pur-
V
R/W
H
5
0
R/W
S
4
0
Atmel ATA6612/ATA6613
R/W
V
3
0
R/W
N
2
0
R/W
1
Z
0
R/W
C
0
0
SREG
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