ATA6613P-PLPW Atmel, ATA6613P-PLPW Datasheet - Page 208

• Manufacturer Part Number: ATA6613P-PLPW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLPW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.17.7
6.17.7.1
Figure 6-73. Start Bit Sampling
6.17.7.2
208
Atmel ATA6612/ATA6613
(U2X = 1)
(U2X = 0)
Asynchronous Data Reception
Sample
Sample
RxD
Asynchronous Clock Recovery
Asynchronous Data Recovery
0
0
IDLE
0
The USART includes a clock recovery and a data recovery unit for handling asynchronous
data reception. The clock recovery logic is used for synchronizing the internally generated
baud rate clock to the incoming asynchronous serial frames at the RxDn pin. The data recov-
ery logic samples and low pass filters each incoming bit, thereby improving the noise immunity
of the Receiver. The asynchronous reception operational range depends on the accuracy of
the internal baud rate clock, the rate of the incoming frames, and the frame size in number of
bits.
The clock recovery logic synchronizes internal clock to the incoming serial frames.
illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16
times the baud rate for Normal mode, and eight times the baud rate for Double Speed mode.
The horizontal arrows illustrate the synchronization variation due to the sampling process.
Note the larger time variation when using the Double Speed mode (U2Xn = 1) of operation.
Samples denoted zero are samples done when the RxDn line is idle (i.e., no communication
activity).
When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line,
the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as
shown in the figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode,
and samples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes
on the figure), to decide if a valid start bit is received. If two or more of these three samples
have logical high levels (the majority wins), the start bit is rejected as a noise spike and the
Receiver starts looking for the next high to low-transition. If however, a valid start bit is
detected, the clock recovery logic is synchronized and the data recovery can begin. The syn-
chronization process is repeated for each start bit.
When the receiver clock is synchronized to the start bit, the data recovery can begin. The data
recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight
states for each bit in Double Speed mode.
data bits and the parity bit. Each of the samples is given a number that is equal to the state of
the recovery unit.
1
1
2
3
2
4
5
3
6
7
4
8
START
9
5
10
Figure 6-74 on page 209
11
6
12
13
7
14
15
8
16
shows the sampling of the
1
1
2
BIT 0
9111H–AUTO–01/11
3
2
Figure 6-73