ATA6613P-PLPW Atmel, ATA6613P-PLPW Datasheet - Page 110

• Manufacturer Part Number: ATA6613P-PLPW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLPW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.11.2
6.11.3
110
Atmel ATA6612/ATA6613
External Interrupt Mask Register – EIMSK
External Interrupt Flag Register – EIFR
• Bit 7..2 – Res: Reserved Bits
• Bit 1 – INT1: External Interrupt Request 1 Enable
• Bit 0 – INT0: External Interrupt Request 0 Enable
• Bit 7..2 – Res: Reserved Bits
• Bit 1 – INTF1: External Interrupt Flag 1
• Bit 0 – INTF0: External Interrupt Flag 0
Read/Write
Initial Value
Read/Write
Initial Value
These bits are unused bits in the Atmel
zero.
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the
external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)
in the External Interrupt Control Register A (EICRA) define whether the external interrupt
is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin
will cause an interrupt request even if INT1 is configured as an output. The corresponding
interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector.
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the
external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00)
in the External Interrupt Control Register A (EICRA) define whether the external interrupt
is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin
will cause an interrupt request even if INT0 is configured as an output. The corresponding
interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.
These bits are unused bits in the Atmel ATA6612/ATA6613, and will always read as zero.
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1
becomes set (one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU
will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt rou-
tine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This
flag is always cleared when INT1 is configured as a level interrupt.
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0
becomes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU
will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt rou-
tine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This
flag is always cleared when INT0 is configured as a level interrupt.
Bit
Bit
R
7
–
R
0
7
–
0
R
R
6
–
0
6
–
0
R
5
–
0
R
5
–
0
R
4
–
0
R
4
–
0
®
ATA6612/ATA6613, and will always read as
R
3
–
0
R
3
–
0
R
2
–
0
R
2
–
0
INTF1
INT1
R/W
R/W
1
0
1
0
INTF0
INT0
R/W
R/W
9111H–AUTO–01/11
0
0
0
0
EIMSK
EIFR