ATA6613P-PLPW Atmel, ATA6613P-PLPW Datasheet - Page 191

MCU W/LIN TXRX REG WTCHDG 48-QFN

ATA6613P-PLPW

Manufacturer Part Number
ATA6613P-PLPW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet

Specifications of ATA6613P-PLPW

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
6.16.1.4
6.16.1.5
9111H–AUTO–01/11
SPI Status Register – SPSR
SPI Data Register – SPDR
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the reg-
ister causes the Shift Register Receive buffer to be read.
• Bit 7 – SPIF: SPI Interrupt Flag
• Bit 6 – WCOL: Write COLlision Flag
• Bit 5..1 – Res: Reserved Bits
• Bit 0 – SPI2X: Double SPI Speed Bit
Initial Value
Read/Write
Initial Value
Read/Write
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE
in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when
the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is
cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI
Data Register (SPDR).
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with
WCOL set, and then accessing the SPI Data Register.
These bits are reserved bits in the Atmel
zero.
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when
the SPI is in Master mode (see
SCK period will be two CPU clock periods. When the SPI is configured as Slave, the SPI is
only guaranteed to work at fosc/4 or lower.
The SPI interface on the Atmel
EEPROM downloading or uploading. See
gramming and verification.
Bit
Bit
MSB
SPIF
R/W
X
R
7
7
0
WCOL
R/W
X
6
R
6
0
R/W
X
5
R
®
5
0
ATA6612/ATA6613 is also used for program memory and
Table 6-69 on page
R/W
X
4
R
4
0
Atmel ATA6612/ATA6613
“Serial Downloading” on page 315
®
ATA6612/ATA6613 and will always read as
R/W
3
X
R
3
0
190). This means that the minimum
R/W
X
2
R
2
0
R/W
1
X
R
1
0
SPI2X
LSB
R/W
R/W
X
0
0
0
for serial pro-
Undefined
SPDR
SPSR
191

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