ATA6613P-PLPW Atmel, ATA6613P-PLPW Datasheet - Page 190

• Manufacturer Part Number: ATA6613P-PLPW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLPW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

190
Atmel ATA6612/ATA6613
Table 6-67.
Table 6-68.
Table 6-69.
• Bit 4 – MSTR: Master/Slave Select
• Bit 3 – CPOL: Clock Polarity
• Bit 2 – CPHA: Clock Phase
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
This bit selects Master SPI mode when written to one, and Slave SPI mode when written
logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will
be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to
re-enable SPI Master mode.
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK
is low when idle. Refer to
tionality is summarized below:
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading
(first) or trailing (last) edge of SCK. Refer to
The CPOL functionality is summarized below:
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock
frequency f
SPI2X
0
0
0
0
1
1
1
1
CPOL
CPHA
0
1
0
1
CPOL Functionality
CPHA Functionality
Relationship Between SCK and the Oscillator Frequency
osc
is shown in the following table:
SPR1
0
0
1
1
0
0
1
1
Figure 6-67
Leading Edge
Leading Edge
Sample
Falling
Rising
Setup
and
SPR0
0
1
0
1
0
1
0
1
Figure 6-68
Figure 6-67
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
for an example. The CPOL func-
and
Figure 6-68
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
for an example.
9111H–AUTO–01/11