HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 99

• Manufacturer Part Number: HW-SPAR3E-SK-US-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-US-G

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1507

Spartan-3E FPGA Starter Kit Board User Guide
UG230 (v1.2) January 20, 2011
R
Insert Jumper on JP8 and Hold PROG_B Low
Table 12-2: Cable Connections to J12 Header
The JTAG parallel programming cable directly accesses the SPI Flash pins. To avoid signal
contention with the FPGA, ensure that the connecting FPGA pins are high-impedance.
Force the FPGA’s PROG_B pin Low by installing a jumper on JP8, next to the PROG push
button, as shown in
surrounding landmarks.
Re-apply power to the Spartan-3E Starter Kit board and program the SPI Flash.
a) No Jumper: FPGA Operational (default)
J12 Header Label
JTAG3 Cable Label
Flying Leads Label
Figure 12-16: Installing the JP8 Jumper Holds the FPGA in Configuration State
Cable and Labels
Figure 12-15: Attaching a JTAG Parallel Programming Cable to the Board
a) JTAG3 Parallel Connector
PROG
GND
JP8
Figure
PROG
www.xilinx.com
12-16. See
PROG
TMS/
TMS
SEL
Figure 12-3, page 92
TDI/
DIN
SDI
TDI
b) Jumper Installed: FPGA Held in
Configuration State, I/Os in High Impedance
b) Parallel Cable III or Parallel Cable IV
DONE
TDO/
SDO
TDO
with Flying Leads
Connections
PROG
GND
to locate jumper JP8 and
TCK/
CCLK
JP8
TCK
SCK
Configuring from SPI Flash
PROG
GND/
GND
GND
GND
UG230_c15_14_030206
UG230_c15_15_030206
VREF/
VREF
VCC
VCC
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