HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 105

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HW-SPAR3E-SK-US-G

Manufacturer Part Number
HW-SPAR3E-SK-US-G
Description
KIT STARTER SPARTAN-3E
Manufacturer
Xilinx Inc
Datasheets

Specifications of HW-SPAR3E-SK-US-G

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1507
DDR SDRAM
Spartan-3E FPGA Starter Kit Board User Guide
UG230 (v1.2) January 20, 2011
LTC3412
5.0V
R
Figure 13-1: FPGA Interface to Micron 512 Mbit DDR SDRAM
The Spartan
Technology DDR SDRAM (MT46V32M16) with a 16-bit data interface, as shown in
Figure
FPGA. I/O Bank 3 and the DDR SDRAM are both powered by 2.5V, generated by an
LTC3412 regulator from the board’s 5V supply input. The 1.25V reference voltage,
common to the FPGA and DDR SDRAM, is generated using a resistor voltage divider from
the 2.5V rail.
VREF
VCCO_3
(B9) GCLK9
SD_CK_FB
13-1. All DDR SDRAM interface pins connect to the FPGA’s I/O Bank 3 on the
1.25V
2.5V
Spartan-3E FPGA
®
-3E FPGA Starter Kit boards includes a 512 Mbit (32M x 16) Micron
See Table
See Table
See Table
(G3)
(C1)
(C2)
(D1)
(K4)
(K3)
(L6)
(J1)
(J2)
(J4)
(J5)
www.xilinx.com
SD_A<12:0>
SD_DQ<15:0>
SD_BA<1:0>
SD_RAS
SD_CAS
SD_WE
SD_UDM
SD_LDM
SD_UDQS
SD_LDQS
SD_CS
SD_CKE
SD_CK_N
SD_CK_P
Micron 512 Mb DDR SDRAM
A[12:0]
DQ[15:0]
BA[1:0]
RAS#
CAS#
WE#
UQM
LQM
UDQS
LDQS
CS#
CKE
CK#
CK
MT46V32M16
Chapter 13
(32Mx16)
VDDQ
VREF
VDD
UG230_c13_01_022406
105

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