HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 22

• Manufacturer Part Number: HW-SPAR3E-SK-US-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-US-G

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1507

Chapter 3: Clock Sources
Clock Connections
Voltage Control
50 MHz On-Board Oscillator
Auxiliary Clock Oscillator Socket
SMA Clock Input or Output Connector
UCF Constraints
22
Location
Each of the clock inputs connect directly to a global buffer input in I/O Bank 0, along the
top of the FPGA. As shown in
an associated DCM.
Table 3-1: Clock Inputs and Associated Global Buffers and DCMs
The voltage for all I/O pins in FPGA I/O Bank 0 is controlled by jumper JP9.
Consequently, these clock resources are also controlled by jumper JP9. By default, JP9 is set
for 3.3V. The on-board oscillator is a 3.3V device and might not perform as expected when
jumper JP9 is set for 2.5V.
The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle. The oscillator
is accurate to
The provided 8-pin socket accepts clock oscillators that fit the 8-pin DIP footprint. Use this
socket if the FPGA application requires a frequency other than 50 MHz. Alternatively, use
the FPGA’s Digital Clock Manager (DCM) to generate or synthesize other frequencies from
the on-board 50 MHz oscillator.
To provide a clock from an external source, connect the input clock signal to the SMA
connector. The FPGA can also generate a single-ended clock output or other high-speed
signal on the SMA clock connector for an external device.
The clock input sources require two different types of constraints. The location constraints
define the I/O pin assignments and I/O standards. The period constraints define the clock
period—and consequently the clock frequency—and the duty cycle of the incoming clock
signal.
Figure 3-2
I/O pin assignment and the I/O standard used. The settings assume that jumper JP9 is set
for 3.3V. If JP9 is set for 2.5V, adjust the IOSTANDARD settings accordingly.
CLK_50MHZ
Clock Input
CLK_AUX
CLK_SMA
provides the UCF constraints for the three clock input sources, including the
±
2500 Hz or
FPGA Pin
www.xilinx.com
±
50 ppm.
A10
C9
B8
Table
3-1, each of the clock inputs also optimally connects to
Spartan-3E FPGA Starter Kit Board User Guide
Global Buffer
GCLK10
GCLK8
GCLK7
UG230 (v1.2) January 20, 2011
Associated DCM
DCM_X0Y1
DCM_X0Y1
DCM_X1Y1
R