HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 71

• Manufacturer Part Number: HW-SPAR3E-SK-US-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-US-G

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1507

Spartan-3E FPGA Starter Kit Board User Guide
UG230 (v1.2) January 20, 2011
SPI Communication Details
Communication Protocol
R
Table 9-2: Disabled Devices on the SPI Bus
Figure 9-3
received relative to the SPI_SCK clock signal. The bus is fully static and supports clocks
rate up to the maximum of 50 MHz. However, check all timing parameters using the
LTC2624 data sheet if operating at or close to the maximum speed.
After driving the DAC_CS slave select signal Low, the FPGA transmits data on the
SPI_MOSI signal, MSB first. The LTC2624 captures input data (SPI_MOSI) on the rising
edge of SPI_SCK; the data must be valid for at least 4 ns relative to the rising clock edge.
The LTC2624 DAC transmits its data on the SPI_MISO signal on the falling edge of
SPI_SCK. The FPGA captures this data on the next rising SPI_SCK edge. The FPGA must
read the first SPI_MISO value on the first rising SPI_SCK edge after DAC_CS goes Low.
Otherwise, bit 31 is missed.
After transmitting all 32 data bits, the FPGA completes the SPI bus transaction by
returning the DAC_CS slave select signal High. The High-going edge starts the actual
digital-to-analog conversion process within the DAC.
Figure 9-4
DAC. The DAC supports both a 24-bit and 32-bit protocol. The 32-bit protocol is shown.
Inside the D/A converter, the SPI interface is formed by a 32-bit shift register. Each 32-bit
command word consists of a command, an address, followed by data value. As a new
command enters the DAC, the previous 32-bit command word is echoed back to the
master. The response from the DAC can be ignored although it is a useful to confirm
correct communication.
SPI_SS_B
AMP_CS
AD_CONV
SF_CE0
FPGA_INIT_B
SPI_MOSI
Signal
SPI_MISO
SPI_SCK
DAC_CS
shows a detailed example of the SPI bus timing. Each bit is transmitted or
shows the communications protocol required to interface with the LTC2624
Figure 9-3: SPI Communication Waveforms
SPI serial Flash
Programmable pre-amplifier
Analog-to-Digital Converter (ADC)
StrataFlash Parallel Flash PROM
Platform Flash PROM
www.xilinx.com
31
Previous 31
Disabled Device
Previous 30
30
Disable Value
Previous 29
29
SPI Communication
1
1
0
1
0
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