HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 86

• Manufacturer Part Number: HW-SPAR3E-SK-US-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-US-G

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1507

Chapter 11: Intel StrataFlash Parallel NOR Flash PROM
86
Table 11-1: FPGA-to-StrataFlash Connections
Category
Signal Name
StrataFlash
SPI_MISO
SF_BYTE
SF_CE0
SF_D15
SF_D14
SF_D13
SF_D12
SF_D11
SF_D10
SF_STS
SF_WE
SF_OE
SF_D9
SF_D8
SF_D7
SF_D6
SF_D5
SF_D4
SF_D3
SF_D2
SF_D1
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FPGA Pin
Number
M16
M15
N10
R16
R15
R10
D16
D17
C18
C17
P17
P10
B18
M9
N9
U9
R8
R9
V9
T8
P6
Upper 8 bits of a 16-bit
halfword when
StrataFlash is
configured for x16
data
(SF_BYTE=High).
Connects to FPGA
user I/O.
Upper 7 bits of a data byte or lower 8 bits of a
16-bit halfword. Connects to FPGA pins D[7:1]
to support the BPI configuration.
Bit 0 of data byte and 16-bit halfword.
Connects to FPGA pin D0/DIN to support the
BPI configuration. Shared with other SPI
peripherals and Platform Flash PROM.
StrataFlash Chip Enable. Connects to FPGA
pin LDC0 to support the BPI configuration.
StrataFlash Write Enable. Connects to FPGA
pin HDC to support the BPI configuration.
StrataFlash Chip Enable. Connects to FPGA
pin LDC1 to support the BPI configuration.
StrataFlash Byte Enable. Connects to FPGA pin
LDC2 to support the BPI configuration.
StrataFlash Status signal. Connects to FPGA
user-I/O pin.
Spartan-3E FPGA Starter Kit Board User Guide
0: x8 data
1: x16 data
UG230 (v1.2) January 20, 2011
Function
Signals SF_D<11:8>
connect to character
LCD pins DB[7:4].
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R