HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 76

• Manufacturer Part Number: HW-SPAR3E-SK-US-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-US-G

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1507

Chapter 10: Analog Capture Circuit
Digital Outputs from Analog Inputs
76
REFAB
REFCD
(N10)
(E18)
(3.3V)
(2.5V)
VINA
VINB
GND
(3.3V)
VCC
Spartan-3E FPGA
Header J7
(U16)
(P11)
(N7)
(P7)
(T4)
The analog capture circuit converts the analog voltage on VINA or VINB and converts it to
a 14-bit digital representation, D[13:0], as expressed by
The GAIN is the current setting loaded into the programmable pre-amplifier. The various
allowable settings for GAIN and allowable voltages applied to the VINA and VINB inputs
appear in
The reference voltage for the amplifier and the ADC is 1.65V, generated via a voltage
divider shown in
VINA or VINB.
The maximum range of the ADC is ±1.25V, centered around the reference voltage, 1.65V.
Hence, 1.25V appears in the denominator to scale the analog input accordingly.
AMP_SHDN
AMP_DOUT
AD_CONV
SPI_MOSI
SPI_MISO
REF = 1.65V
AMP_CS
SPI_SCK
Figure 10-2: Detailed View of Analog Capture Circuit
Table
10-2.
LTC 6912-1 AMP
D 13:0
DIN
CS/LD
SCK
SHDN
Figure
[
0
SPI Control Interface
A GAIN
]
1
10-2. Consequently, 1.65V is subtracted from the input voltage on
A
=
www.xilinx.com
2
GAIN
3
0
B GAIN
1
B
2
×
3
(
----------------------------------- -
V
DOUT
IN
1.25V
–
1.65V
Spartan-3E FPGA Starter Kit Board User Guide
)
×
8192
Equation
SCK
CONV
LTC 1407A-1 ADC
Channel 0
Channel 1
CHANNEL 1 CHANNEL 0
0
A/D
A/D
UG230 (v1.2) January 20, 2011
SPI Control Interface
...
10-1.
13
14
14
0
...
Equation 10-1
UG230_c10_02_022306
13
SDO
R