HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 62

• Manufacturer Part Number: HW-SPAR3E-SK-US-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-US-G

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1507

Chapter 7: RS-232 Serial Ports
UCF Location Constraints
62
Figure 7-1
FPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim device,
which in turn, converts the logic value to the appropriate RS-232 voltage level. Likewise,
the Maxim device converts the RS-232 serial input data to LVTTL levels for the FPGA. A
series resistor between the Maxim output pin and the FPGA’s RXD pin protects against
accidental logic conflicts.
Hardware flow control is not supported on the connector. The port’s DCD, DTR, and DSR
signals connect together, as shown in
connect together.
Figure 7-2
respectively, including the I/O pin assignment and the I/O standard used.
NET "RS232_DTE_RXD"
NET "RS232_DTE_TXD"
NET "RS232_DCE_RXD"
NET "RS232_DCE_TXD"
Figure 7-2: UCF Location Constraints for DTE RS-232 Serial Port
Figure 7-3: UCF Location Constraints for DCE RS-232 Serial Port
shows the connection between the FPGA and the two DB9 connectors. The
and
Figure 7-3
provide the UCF constraints for the DTE and DCE RS-232 ports,
www.xilinx.com
LOC
LOC
LOC
LOC
= "M13" |
= "M14" |
= "U8"
= "R7"
Figure
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
7-1. Similarly, the port’s RTS and CTS signals
Spartan-3E FPGA Starter Kit Board User Guide
= LVTTL |
= LVTTL |
= LVTTL ;
= LVTTL ;
UG230 (v1.2) January 20, 2011
DRIVE
DRIVE
= 8 |
= 8 |
SLEW
SLEW
= SLOW ;
= SLOW ;
R