HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 89

• Manufacturer Part Number: HW-SPAR3E-SK-US-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-US-G

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1507

Setting the FPGA Mode Select Pins
Related Resources
Spartan-3E FPGA Starter Kit Board User Guide
UG230 (v1.2) January 20, 2011
Control
R
Figure 11-4
I/O pin assignment and the I/O standard used.
Set the FPGA configuration mode pins for either BPI Up or BPI down mode, as shown in
Table
Table 11-4: Selecting BPI-Up or BPI-Down Configuration Modes (Header J30 in
Figure
•
Configuration
BPI Up
BPI Down
Intel J3 StrataFlash Data Sheet
http://www.numonyx.com/en-
US/MemoryProducts/NOR/Pages/NumonyxEmbeddedFlashMemoryJ3.aspx
NET
NET
NET
NET
NET
Mode
11-4. See
4-2)
Figure 11-4: UCF Location Constraints for StrataFlash Control Pins
"SF_BYTE"
"SF_CE0"
"SF_OE"
"SF_STS"
"SF_WE"
provides the UCF constraints for the StrataFlash control pins, including the
Mode Pins
M2:M1:M0
LOC
LOC
LOC
LOC
LOC
0:1:0
0:1:1
= "C17" |
= "D16" |
= "C18" |
= "B18" |
= "D17" |
www.xilinx.com
FPGA starts at address 0 and
increments through address space.
The CPLD controls address lines
A[24:20] during BPI configuration.
FPGA starts at address 0xFF_FFFF
and decrements through address
space. The CPLD controls address
lines A[24:20] during BPI
configuration.
FPGA Configuration Image in
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
StrataFlash
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
Setting the FPGA Mode Select Pins
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
= 4 |
= 4 |
= 4 |
= 4 |
= 4 |
Jumper Settings
M0
M1
M2
M0
M1
M2
SLEW
SLEW
SLEW
SLEW
SLEW
J30
J30
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
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