HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 144

no-image

HW-SPAR3E-SK-US-G

Manufacturer Part Number
HW-SPAR3E-SK-US-G
Description
KIT STARTER SPARTAN-3E
Manufacturer
Xilinx Inc
Datasheets

Specifications of HW-SPAR3E-SK-US-G

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1507
Appendix A: Schematics
FPGA I/O Banks 0 and 1, Oscillators
144
IC10B0 represents the connections to I/O Bank 0 on the FPGA. The VCCO input to Bank 0
is 3.3V by default, but can be set to 2.5V using jumper JP9.
IC10B1 represents the connections to I/O Bank 1 on the FPGA.
IC17 is the 50 MHz clock oscillator.
IC16 is an 8-pin DIP socket to insert an alternate clock oscillator with a different frequency.
www.xilinx.com
Chapter 3, “Clock Sources,”
Spartan-3E FPGA Starter Kit Board User Guide
UG230 (v1.2) January 20, 2011
for additional information.
R

Related parts for HW-SPAR3E-SK-US-G