HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 114

• Manufacturer Part Number: HW-SPAR3E-SK-US-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-US-G

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1507

Chapter 14: 10/100 Ethernet Physical Layer Interface
UCF Location Constraints
Related Resources
114
The hardware evaluation versions of the Ethernet MAC cores operate for approximately
eight hours in silicon before timing out. To order the full version of the core, visit the Xilinx
website at:
Figure 14-4
the I/O pin assignment and the I/O standard used.
•
•
•
•
http://www.xilinx.com/products/ipcenter/OPB_10_100_Lite.htm
Standard Microsystems SMSC LAN83C185 10/100 Ethernet PHY
http://www.smsc.com/main/catalog/lan83c185.html
Xilinx OPB Ethernet Media Access Controller (EMAC) (v1.02a)
www.xilinx.com/support/documentation/ip_documentation/opb_ethernet.pdf
Xilinx OPB Ethernet Lite Media Access Controller (v1.01a)
The Ethernet Lite MAC controller core uses fewer FPGA resources and is ideal for
applications the do not require support for interrupts, back-to-back data transfers, and
statistics counters.
www.xilinx.com/support/documentation/ip_documentation/opb_ethernetlite.pdf
EDK Documentation
http://www.xilinx.com/tools/embedded.htm
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
Figure 14-4: UCF Location Constraints for 10/100 Ethernet PHY Inputs
"E_COL"
"E_CRS"
"E_MDC"
"E_MDIO"
"E_RX_CLK"
"E_RX_DV"
"E_RXD<0>"
"E_RXD<1>"
"E_RXD<2>"
"E_RXD<3>"
"E_RXD<4>"
"E_TX_CLK"
"E_TX_EN"
"E_TXD<0>"
"E_TXD<1>"
"E_TXD<2>"
"E_TXD<3>"
"E_TXD<4>"
provides the UCF constraints for the 10/100 Ethernet PHY interface, including
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
= "P9"
= "U5"
= "P15" |
= "R11" |
= "T15" |
= "R5"
= "T5"
= "R6"
= "U6"
= "U13" |
= "V3"
= "V2"
= "V8"
= "T11" |
= "U11" |
= "V14" |
= "U14" |
= "T7"
www.xilinx.com
|
|
|
|
|
|
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
Spartan-3E FPGA Starter Kit Board User Guide
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 ;
= LVCMOS33 ;
= LVCMOS33 ;
= LVCMOS33 ;
= LVCMOS33 ;
= LVCMOS33 ;
= LVCMOS33 ;
= LVCMOS33 ;
= LVCMOS33 ;
= LVCMOS33 ;
UG230 (v1.2) January 20, 2011
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
= SLOW
= SLOW
= SLOW
= SLOW
= SLOW
= SLOW
= SLOW
= SLOW
|
|
|
|
|
|
|
|
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
= 8 ;
= 8 ;
= 8 ;
= 8 ;
= 8 ;
= 8 ;
= 8 ;
= 8 ;
R