HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 64

• Manufacturer Part Number: HW-SPAR3E-SK-US-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-US-G

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1507

Chapter 8: PS/2 Mouse/Keyboard Port
Keyboard
64
organized differently for a mouse and keyboard. Furthermore, the keyboard interface
allows bidirectional data transfers so the host device can illuminate state LEDs on the
keyboard.
The PS/2 bus timing appears in
only driven when data transfers occur; otherwise they are held in the idle state at logic
High. The timing defines signal requirements for mouse-to-host communications and
bidirectional keyboard communications. As shown in
mouse writes a bit on the data line when the clock signal is High, and the host reads the
data line when the clock signal is Low.
Table 8-2: PS/2 Bus Timing
The keyboard uses open-collector drivers so that either the keyboard or the host can drive
the two-wire bus. If the host never sends data to the keyboard, then the host can use simple
input pins.
A PS/2-style keyboard uses scan codes to communicate key press data. Nearly all
keyboards in use today are PS/2 style. Each key has a single, unique scan code that is sent
whenever the corresponding key is pressed. The scan codes for most keys appear in
Figure
If the key is pressed and held, the keyboard repeatedly sends the scan code every 100 ms or
so. When a key is released, the keyboard sends an “F0” key-up code, followed by the scan
code of the released key. The keyboard sends the same scan code, regardless if a key has
different shift and non-shift characters and regardless whether the Shift key is pressed or
not. The host determines which character is intended.
Some keys, called extended keys, send an “E0” ahead of the scan code and furthermore,
they might send more than one scan code. When an extended key is released, an “E0 F0”
key-up code is sent, followed by the scan code.
Symbol
T
T
T
HLD
CK
SU
8-3.
Clock High or Low Time
Data-to-clock Setup Time
Clock-to-data Hold Time
DATA (PS2D)
CLK (PS2C)
Figure 8-2: PS/2 Bus Timing Waveforms
www.xilinx.com
Parameter
Edge 0
T
Table 8-2
SU
'0' start bit
and
Spartan-3E FPGA Starter Kit Board User Guide
T
Figure
T
CK
HLD
T
CK
8-2. The clock and data signals are
Figure
'1' stop bit
30 μs
Min
5 μs
5 μs
UG230_c8_02_021806
8-2, the attached keyboard or
UG230 (v1.2) January 20, 2011
Edge 10
50 μs
25 μs
25 μs
Max
R