HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 109

• Manufacturer Part Number: HW-SPAR3E-SK-US-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-US-G

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1507

Related Resources
Spartan-3E FPGA Starter Kit Board User Guide
UG230 (v1.2) January 20, 2011
Control
Reserve FPGA VREF Pins
R
Figure 13-4
control pins, including the I/O pin assignment and the I/O standard used.
Five pins in I/O Bank 3 are dedicated as voltage reference inputs, VREF. These pins cannot
be used for general-purpose I/O in a design. Prohibit the software from using these pins
with the constraints provided in
5i
•
•
•
Xilinx Embedded Design Kit (EDK)
http://www.xilinx.com/tools/platform.htm
MT46V32M16 (32M x 16) DDR SDRAM Data Sheet
http://download.micron.com/pdf/datasheets/dram/ddr/512MBDDRx4x8x16.pdf
MicroBlaze OPB Double Data Rate (DDR) SDRAM Controller (v2.00b)
http://www.xilinx.com/support/documentation/ip_documentation/opb_ddr.pdf
# Prohibit VREF pins
CONFIG PROHIBIT
CONFIG PROHIBIT
CONFIG PROHIBIT
CONFIG PROHIBIT
CONFIG PROHIBIT
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
# Path to allow connection to top DCM connection
NET
Figure 13-4: UCF Location Constraints for DDR SDRAM Control Pins
Figure 13-5: UCF Location Constraints for StrataFlash Control Pins
"SD_BA<0>"
"SD_BA<1>"
"SD_CAS"
"SD_CK_N"
"SD_CK_P"
"SD_CKE"
"SD_CS"
"SD_LDM"
"SD_LDQS"
"SD_RAS"
"SD_UDM"
"SD_UDQS"
"SD_WE"
"SD_CK_FB"
provides the User Constraint File (UCF) constraints for the DDR SDRAM
= D2;
= G4;
= J6;
= L5;
= R4;
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
www.xilinx.com
= "K5" |
= "K6" |
= "C2" |
= "J4" |
= "J5" |
= "K3" |
= "K4" |
= "J2" |
= "L6" |
= "C1" |
= "J1" |
= "G3" |
= "D1" |
= "B9" |
Figure
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
13-5.
= SSTL2_I ;
= SSTL2_I ;
= SSTL2_I ;
= SSTL2_I ;
= SSTL2_I ;
= SSTL2_I ;
= SSTL2_I ;
= SSTL2_I ;
= SSTL2_I ;
= SSTL2_I ;
= SSTL2_I ;
= SSTL2_I ;
= SSTL2_I ;
= LVCMOS33 ;
Related Resources
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