HW-V5-ML550-UNI-G Xilinx Inc, HW-V5-ML550-UNI-G Datasheet - Page 85

• Manufacturer Part Number: HW-V5-ML550-UNI-G
• Description: EVALUATION PLATFORM VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr
• Type: FPGAr

Specifications of HW-V5-ML550-UNI-G

• Contents: Development Platform, Power Supply, Loopback Board, CompactFlash Card, software and documentation
• Silicon Manufacturer: Xilinx
• Features: 64M X 8 DDR SDRAM Memory, Six Samtec LVDS Connectors
• Kit Contents: Board, Cable, PSU, CD, Docs
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VLX50T-FFG1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Virtex™-5 LXT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ML550 Networking Interfaces Platform
UG202 (v1.4) April 18, 2008
10
9
8
7
6
5
4
3
2
1
Array Connector Numbering
UCF Information
R
A
Connector J32
B
C
#
# Bank 0 / LCD-BUS
#
# NET "
# NET "
# NET "
# NET "
# NET "
# NET "
# NET "
# NET "
# NET "
# NET "
# NET "
# NET "
# NET "
#
D
E
Figure C-12: LCD Connections (Bank 0)
F
" LOC ="F24 ";
" LOC ="F23 ";
" LOC ="E23 ";
" LOC ="E22 ";
" LOC ="G22 ";
" LOC ="F22 ";
" LOC ="F21 ";
" LOC ="G23 ";
" LOC ="D24 ";
" LOC ="C24 ";
" LOC ="H21 ";
" LOC ="G21 ";
" LOC ="H22 ";
Bank 0
G
H
www.xilinx.com
I
# LCD_D7
# LCD_D6
# LCD_D5
# LCD_D4
# LCD_D3
# LCD_D2
# LCD_D1
# LCD_D0
# LCD_RST
# LCD_CS1B
# LCD_RSEL
# LCD_RW
# LCD_ENA
E10
D9
D7
D5
D3
D1
E8
E6
E4
E2
F5
F3
F1
Connector Pin
LCD_D0
LCD_D4
LCD_D5
LCD_D6
LCD_D7
LCD_RST
LCD_D1
LCD_D2
LCD_D3
LCD_ENA
LCD_R/W
LCD_RSEL
LCD_CS1B
Hardware Schematic Diagram
FPGA Pin
UG202_C_12_050906
IO0L02N
IO0L02P
IO0L03N
IO0L03P
IO0L06P
IO0L07N
IO0L07P
IO0L05
IO0L08N
IO0L08P
IO0L09N
IO0L09P
IO0L06N
G23
E22
E23
F23
F24
D24
F21
F22
G22
H22
G21
H21
C24
85